Chang Hee Han

Electrical Characteristics and Thermal Stability of W, WN x , and TiN Barriers in Metal / Ta2 O 5 / Si Gate Devices

Tantalum pentoxide was adopted as gate dielectric for obtaining gate oxide with less than 3.0 nm of SiO 2 equivalent thickness and low leakage current. Physical vapor deposited (PVD) W, PVD WN x , PVD TiN, or TiCl 4 -based chemical vapor deposited (CVD) TiN was used as gate/barrier material on Ta 2 O 5 . Thermal stability and electrical property of each harrier were evaluated at elevated temperature of 900°C. W and WN x barriers show much lower leakage current than TiN barriers at both low and high fields. Leakage current is lower with WN x barrier than with W barrier at high field. The breakdown characteristics of W and WN x barriers are noticeably improved after annealing at 900°C because of the recovery from sputtering damage. The breakdown characteristic of WN x is superior to W and this is thought to come from the incorporation of nitrogen into the Ta 2 O 5 layer. Breakdown property is not degraded significantly in the samples with PVD TiN barrier. However, the samples with CVD TiN barrier show significant degradation in electrical property at the elevated temperature. Microvoids are formed in Ta 2 O 5 layer along the TiN/Ta 2 O 5 interface in PVD TiN sample after annealing at 900°C. Ta diffuses into the TiN layer leaving voids behind. Ta 2 O 5 is more severely damaged in the CVD TiN sample. Diffusion of Ta and O becomes significant in this sample after annealing. The Cl content is also much higher in CVD TiN samples than PVD TiN samples. Thus residual Cl is considered to be the main reason for the degradation of Ta 2 O 5 in the metal/Ta 2 O 5 /Si devices containing CVD TiN as a barrier material.

In situ barrier formation using rapid thermal annealing of a tungsten nitride/polycrystalline silicon structure

This letter describes the use of rapid thermal annealing (RTA) to form a barrier layer applicable to the gate electrode in dynamic random access memory devices with a stacked structure [tungsten nitride (WNx)/polycrystalline Si (poly-Si)]. After RTA, the reactively sputtered amorphous WNx film on the poly-Si was transformed to a low-resistive α-phase W and nitrogen-segregated layer. Most of the nitrogen in the WNx film was dissipated and a relatively small amount of the nitrogen was segregated at the interface of the α-phase W and poly-Si. The segregated layer was estimated to be 2 nm thick and revealed a silicon nitride (Si–N) bonding status. More importantly, we found that this thin segregated layer successfully protected the formation of tungsten silicide, even after RTA at 1000 °C for 2 min in a hydrogen environment.

In-situ barrier formation for high reliable W/barrier/poly-Si gate using denudation of WN/sub x/ on polycrystalline Si

We found that rapid thermal annealing treatment of amorphous WN/sub x//poly-Si resulted in denudation of nitrogen atoms with formation of low resistivity W and high reliable in situ barrier layer, simultaneously. Furthermore, electrical properties of denuded-WN/sub x//poly-Si gate were superior to those of conventional W/WN/sub x//poly-Si gate after selective oxidation and post heat-treatment.

The effect of Co incorporation on electrical characteristics of n/sup +//p shallow junction formed by dopant implantation into CoSi/sub 2/ and anneal

The impact of Co incorporation on the electrical characteristics has been investigated in n/sup +//p junction formed by dopant implantation into CoSi/sub 2/ and drive-in anneal. The junctions were formed by As/sup +/ (30 or 40 keV, 1/spl times/10/sup 16/ cm/sup -2/) implantation into 35 nm-thick CoSi/sub 2/ followed by drive-in annealing at 900/spl deg/C for 30 s in an N/sub 2/ ambient. Deeper junction implanted by As/sup +/ at 40 keV was not influenced by the Co incorporation. However, for shallower junction implanted by As/sup +/ at 30 keV, incorporation of Co atoms increased its leakage current, which were supposed to be dissociated from the CoSi/sub 2/ layer by silicide agglomeration during annealing. The mechanism of such a high leakage current was found to be Poole-Frenkel barrier lowering induced by high density of Co traps.

Degradation of Ta2O5 Gate Dielectric by TiCl4-Based Chemically Vapor Deposited TiN Film in W/TiN/Ta2O5/Si System

Tantalum pentoxide was adopted as a gate dielectric for obtaining gate oxide with less than 3.0 nm SiO2 equivalent thickness and low leakage current. Physical vapor deposited (PVD) TiN or TiCl4-based chemical-vapor-deposited (CVD) TiN was used as the barrier material between the W electrode and Ta2O5 layer. The thermal stability and electrical property of each barrier were evaluated at an elevated temperature of 900?C. In the as-deposited condition and after annealing at 800?C, PVD and CVD TiN show similar electrical properties. However, after annealing at 900?C, CVD TiN barriers show much lower breakdown fields and higher leakage current compared with PVD TiN, indicating that CVD TiN has worse barrier performance than PVD TiN. Microvoids are formed in the Ta2O5 layer along the PVD TiN/Ta2O5 interface after annealing at 900?C. It is found that Ta diffuses into the TiN layer leaving microvoids behind. Ta2O5 is more severely damaged in the CVD TiN system after annealing. The high content of residual Cl in CVD TiN was found to reduce Ta2O5 and generate free Ta and O. Free Ta and O atoms that are generated from the reduction of Ta2O5 diffuse into the TiN layer and hence produce macrovoids and disconnected areas in the Ta2O5 layer. The transmission electron microscopy (TEM) images and secondary ion mass spectrometry (SIMS) depth profiles are in good agreement with the electrical properties of W/TiN/Ta2O5/Si gate devices.

Formation of CoSi2 on various polycrystalline silicon structures and its effects on thermal stability

We have investigated formation of CoSi 2 on various grain sizes of polycrystalline Si (poly-Si) with emphasis on its thermal stability. As the grain size of poly-Si decreases, CoSi 2 phase is formed at lower temperature because of the diffusion of Co atoms along grain boundaries of poly-Si during the rapid thermal annealing process. The enhanced reaction of cobalt with silicon on small-grain-sized poly-Si creates a rough CoSi 2 /poly-Si interface, which becomes thermally unstable. CoSi 2 formed on amorphous Si showed less thermal stability than that found on medium and large grain sized poly-Si.

Improvement of Reverse Leakage Current by Fluorine Implantation in n^+/p Shallow Junctions Diffused from a Cobalt Silicide Layer

The effect of fluorine implantation on reverse leakage current has been investigated in n+/p junctions formed by diffusion from a cobalt silicide layer. Fluorine (F) implantation at a moderate dose and energy improves the junction leakage, but high dose fluorine implantation, above 1×1015 cm-2, degrades junction leakage. Considering that F implantation does not affect the thermal stability of the CoSi2 layer and arsenic concentration profiles, it is conjectured that the highly electronegative and reactive F ions cause deactivation of silicon lattice defects that act as generation centers, thereby reducing leakage. However, F ions in excess may act as defects themselves in silicon rather than reducing the silicon lattice defects, which increases the leakage current.

A Study on Thermal Stability of CoSi2 Employing Novel Fine-Grained Polycrystalline Silicon/CoSi2/Si (001) System

The cobalt silicide/fine-grained polycrystalline silicon (poly-Si) structure has been employed as gate electrodes in silicon-based very large-scale integration circuits. We have constructed a novel fine-grained poly-Si/cobalt silicide/silicon (001) structure to investigate the thermal stability of cobalt silicide at elevated temperatures. The dissociated cobalt atoms are observed to diffuse from fine-grained poly-Si/cobalt silicide and cobalt silicide/silicon (001) interfaces into the fine-grained poly-Si layer through poly-Si grain boundaries and the bulk cobalt silicide layer. The dissociated Si atoms at the cobalt silicide/silicon (001) interface are observed to grow epitaxilly on the silicon (001) substrate. This observation is consistent with previous results for circuits that employed amorphous Si instead of fine-grained poly-Si.

Reaction barrier formation of W/poly-Si gate by NH/sub 3/ rapid thermal annealing applicable to 0.15 /spl mu/m CMOS devices

We found that an NH/sub 3/ rapid thermal annealing of Wi/poly-Si gate above 750/spl deg/C resulted in the formation of a highly reliable in-situ barrier layer and low resistivity W, simultaneously. This barrier layer kept the Wi/poly-Si gate stable up to the elevated temperature of 1000/spl deg/C. Ammonia treated W/poly-Si gate showed a narrow distribution of sheet resistance at a line width of 0.15 /spl mu/m after the post annealing at 900/spl deg/C for 30 min. This W/poly-Si gate was acceptable to apply to 0.15 /spl mu/m CMOS devices without deposition of a barrier layer.

Improvement of Gate Oxide Reliability for Direct Tungsten-Gate Using Denudation of WNx

We investigated a gate oxide reliability of metal-oxide-semiconductor capacitors with W and denuded WNx gate. A 5.5 nm-thick SiO2 was used as gate dielectric. The W gate was deposited by D.C. magnetron sputtering and the denuded WNx gate was formed by N2 annealing following the deposition of WNx. The leakage current and charge-to-breakdown results indicate that the denuded WNx gate shows improved gate oxide reliability comparing with pure W gate. It is believed to be due to the segregation of nitrogen atoms at the interface of W and SiO2 film. It is also observed that the sputtering power must be reduced to improve the roughness of metal/SiO2 interface.