Chang-Hong Shen

Roll-to-roll fabrication of large scale and regular arrays of three-dimensional nanospikes for high efficiency and flexible photovoltaics

Three-dimensional (3-D) nanostructures have demonstrated enticing potency to boost performance of photovoltaic devices primarily owning to the improved photon capturing capability. Nevertheless, cost-effective and scalable fabrication of regular 3-D nanostructures with decent robustness and flexibility still remains as a challenging task. Meanwhile, establishing rational design guidelines for 3-D nanostructured solar cells with the balanced electrical and optical performance are of paramount importance and in urgent need. Herein, regular arrays of 3-D nanospikes (NSPs) were fabricated on flexible aluminum foil with a roll-to-roll compatible process. The NSPs have precisely controlled geometry and periodicity which allow systematic investigation on geometry dependent optical and electrical performance of the devices with experiments and modeling. Intriguingly, it has been discovered that the efficiency of an amorphous-Si (a-Si) photovoltaic device fabricated on NSPs can be improved by 43%, as compared to its planar counterpart, in an optimal case. Furthermore, large scale flexible NSP solar cell devices have been fabricated and demonstrated. These results not only have shed light on the design rules of high performance nanostructured solar cells, but also demonstrated a highly practical process to fabricate efficient solar panels with 3-D nanostructures, thus may have immediate impact on thin film photovoltaic industry.

Fast Programming Metal-Gate Si Quantum Dot Nonvolatile Memory Using Green Nanosecond Laser Spike Annealing

The ultrafast metal-gate silicon quantum-dot (Si-QD) nonvolatile memory (NVM) with program/erase speed of 1 μs under low operating voltages of ± 7 V is achieved by thin tunneling oxide, in situ Si-QD-embedded dielectrics, and metal gate. Selective source/drain activation by green nanosecond laser spike annealing, due to metal-gate as light-blocking layer, responds to low thermal damage on gate structures and, therefore, suppresses re-crystallization/deformation/diffusion of embedded Si-QDs. Accordingly, it greatly sustains efficient charge trapping/de-trapping in numerous deep charge-trapping sites in discrete Si-QDs. Such a gate nanostructure also ensures excellent endurance and retention in the microsecond-operation Si-QD NVM.

Large scale, flexible and three-dimensional quasi-ordered aluminum nanospikes for thin film photovoltaics with omnidirectional light trapping and optimized electrical design

Nanostructured photovoltaics has attracted an enormous amount of attention in recent years owing to its potency for significant device performance enhancement over the conventional technologies. Nonetheless, conventional fabrication approaches for nanostructured scaffolds rely on glass or silicon substrates which are costly, brittle and have limited scalability. Meanwhile, rational design guidelines for optical and electrical performance optimization of solar cells are of urgent need for their practical applications. In this work, flexible and quasi-ordered three-dimensional (3-D) nanospike (NSP) arrays are fabricated on a reasonable large scale with well controlled geometry. Systematic investigations by experiments discovered that photovoltaic devices based on NSPs with optimal geometry can accommodate the trade-off between optical absorption and electrical performance, demonstrating a power conversion efficiency of 7.92%, which is among the highest efficiency reported for single junction a-Si:H solar cells on a flexible substrate. Furthermore, we have demonstrated the superior omnidirectional device performance by utilizing such a 3-D NSP. This unique feature is of paramount importance for practical photovoltaic applications.

Embedded biomimetic nanostructures for enhanced optical absorption in thin-film solar cells

Light-management is critical to thin film solar cells due to their usually limited optical absorption in the active layer. Conventional approaches involve employing separate techniques for anti-reflection and light trapping. Here, we demonstrate an embedded biomimetic nanostructure (EBN) that achieves both effects for hydrogenated amorphous silicon (a-Si:H) solar cells. The fabrication of EBNs is accomplished by patterning an index-matching silicon-nitride layer deposited on a glass substrate using polystyrene nanospheres lithography, followed by reactive ion etching. The profile of EBN is then reproduced layer by layer during the deposition of a-Si:H cells. We show that a solar cell with an optimized EBN exhibits a broadband enhanced external quantum efficiency due to both anti-reflection and light-trapping, with respect to an industrial standard cell using an Asahi U glass substrate which is mostly optimized for light trapping. Overall, the cell with an optimized EBN achieves a large short-circuit current density of 17.74 mA/cm(2), corresponding to a 37.63% enhancement over a flat control cell. The power conversion efficiency is also increased from 5.36% to 8.32%. Moreover, the light management enabled by the EBN remains efficient over a wide range of incident angles up to 60°, which is particularly desirable for real environments with diffused sun light. The novel patterning method is not restricted to a-Si:H solar cells, but is also widely applicable to other thin film materials.

Non-Drude Behavior in Indium-Tin-Oxide Nanowhiskers and Thin Films Investigated by Transmission and Reflection THz Time-Domain Spectroscopy

A comparative study of indium-tin-oxide (ITO) nanowhiskers (NWhs) and thin films as transparent conductors in the terahertz frequency range are conducted. We employ both transmission-type and reflection-type terahertz time-domain spectroscopies (THz-TDTS and THz-TDRS) to explore the far-infrared optical properties of these samples. Their electrical properties, such as plasma frequencies and carrier scattering times, are analyzed and found to be fitted well by the Drude-Smith model over 0.1-1.4 THz. Further, structural and crystalline properties of samples are examined by scanning electron microscopy and X-ray diffraction, respectively. Non-Drude behavior of complex conductivities in ITO NWhs is attributed to carrier scattering from grain boundaries and impurity ions. In ITO thin films, however, the observed non-Drude behavior is ascribed to scattering by impurity ions only. Considering NWhs and thin films with the same height, mobility of the former is ~ 125 cm2V-1s-1, much larger than those of the ITO thin films, ~ 27 cm2 V-1 s-1. This is attributed to the longer carrier scattering time of the NWhs. The dc conductivities ( ~ 250 Ω-1 cm-1) or real conductivities in the THz frequency region of ITO NWhs is, however, lower than those of the ITO thin films ( ~ 800 Ω-1 cm-1) but adequate for use as electrodes. Partly, this is a reflection of the much higher plasma frequencies of thin films. Significantly, the transmittance of ITO NWhs ( ≅ 60%-70%) is much higher ( ≅ 13 times) than those of ITO thin films in the THz frequency range. The underneath basic physics is that the THz radiation can easily propagate through the air-space among NWhs. The superb transmittance and adequate electrical properties of ITO NWhs suggest their potential applications as transparent conducting electrodes in THz devices.

Strength, stiffness, and microstructure of Cu(In,Ga)Se2 thin films deposited via sputtering and co-evaporation

This work examines Cu(In,Ga)Se_2 thin films fabricated by (1) selenization of pre-sputtered Cu-In-Ga and (2) co-evaporation of each constituent. The efficiency disparity between films deposited via these two methods is linked to differences in morphology and microstructure. Atomic force microscopy and scanning electron microscopy show that selenized films have rougher surfaces and poor adhesion to molybdenum back contact. Transmission electron microscopy and electron energy loss spectroscopy revealed multiple voids near the Mo layer in selenized films and a depletion of Na and Se around the voids. Residual stresses in co-evaporated films were found to be ∼1.23 GPa using wafer curvature measurements. Uniaxial compression experiments on 500 nm-diameter nanopillars carved out from co-evaporated films revealed the elastic modulus of 70.4 ± 6.5 GPa. Hertzian contact model applied to nanoindentation data on selenized films revealed the indentation modulus of 68.9 ± 12.4 GPa, which is in agreement with previous reports. This equivalence of the elastic moduli suggests that microstructural differences manifest themselves after the yield point. Typical plastic behavior with two distinct failure modes is observed in the extracted stress-strain results, with the yield strength of 640.9 ± 13.7 MPa for pillars that failed by shearing and 1100.8 ± 77.8 MPa for pillars that failed by shattering.

Improved Efficiency of a Large-Area Cu(In,Ga)Se2 Solar Cell by a Nontoxic Hydrogen-Assisted Solid Se Vapor Selenization Process

A nontoxic hydrogen-assisted solid Se vapor selenization process (HASVS) technique to achieve a large-area (40 × 30 cm(2)) Cu(In,Ga)Se2 (CIGS) solar panel with enhanced efficiencies from 7.1 to 10.8% (12.0% for active area) was demonstrated. The remarkable improvement of efficiency and fill factor comes from improved open circuit voltage (Voc) and reduced dark current due to (1) decreased interface recombination raised from the formation of a widened buried homojunction with n-type Cd(Cu) participation and (2) enhanced separation of electron and hole carriers resulting from the accumulation of Na atoms on the surface of the CIGS film. The effects of microstructural, compositional, and electrical characteristics with hydrogen-assisted Se vapor selenization, including interdiffusion of atoms and formation of buried homojunction, were examined in detail. This methodology can be also applied to CIS (CuInSe2) thin film solar cells with enhanced efficiencies from 5.3% to 8.5% (9.4% for active area) and provides a facile approach to improve quality of CIGS and stimulate the nontoxic progress in the large scale CIGS PV industry.

Monolithic 3D chip integrated with 500ns NVM, 3ps logic circuits and SRAM

For the first time, a sequentially processed sub-50nm monolithic 3D IC with integrated logic/NVM circuits and SRAM is demonstrated using multiple layers of ultrathin-body (UTB) MOSFET-based circuits interconnected through 300nm-thick interlayer dielectric (ILD). High-performance sub-50nm UTB MOSFETs using deposited ultra-flat and ultra-thin (20nm) epi-like Si enable across-layer and in-layer high-speed 3ps logic circuits and 1-T 500ns plasma-MONOS NVMs as well as 6T SRAMs with static noise margin (SNM) of 280 mV and reduced footprint by 25%. Closely stacked monolithic 3D circuits envision advanced high-performance, rich function, and low power intelligent mobile devices.

Improvement of peak‐to‐valley ratio by the incorporation of the InAs layer into the GaSb/AlSb/GaSb/AlSb/InAs double barrier resonant interband tunneling structure

InAs blocking layer is incorporated into the GaSb/AlSb/GaSb/AlSb/InAs double barrier resonant interband tunneling structure to improve the peak‐to‐valley ratios. It is found the ratio rises to 21 at room temperature and the peak current density keeps nearly constant for InAs layer reaches 30 A and then both of them decreases with the increase of InAs thickness. However, while the InAs blocking layer further increases to 240 A, the I‐V characteristic shows multiple negative differential resistance behavior. These interesting phenomena can be modeled to be due to the coupling effect of InAs blocking layer and GaSb well layer.

Record-high 121/62 μA/μm on-currents 3D stacked epi-like Si FETs with and without metal back gate

A sequential layered integration technology that can fabricate 3D stackable epi-like Si FETs with and without metal back gate (MBG) under sub-400°C are proposed in this article. With laser crystallized epi-like Si and CMP thinning processes for channel fabrication, 3D stackable ultra thin body (UTB) n/p-MOSFETs with low-subthreshold swings (88 and 121 mV/dec.) and high on-currents (121 and 62 μA/μm) are demonstrated. With additional metal back gate structure, UTB devices can be desirably operated in a positive or negative threshold voltage range with γ values of 0.51 (n-MOSFETs) and 0.56 (p-MOSFETs) for favoring its applications in 3D logic circuits. In addition, such thin and high quality channel and metal back gate scheme is not only promising for conventional p-n junction device but also junctionless (JL) scheme, which can simplify the fabrication and achieve further scaling.