Hsing-Hsiang Wang

Monolithic 3D chip integrated with 500ns NVM, 3ps logic circuits and SRAM

For the first time, a sequentially processed sub-50nm monolithic 3D IC with integrated logic/NVM circuits and SRAM is demonstrated using multiple layers of ultrathin-body (UTB) MOSFET-based circuits interconnected through 300nm-thick interlayer dielectric (ILD). High-performance sub-50nm UTB MOSFETs using deposited ultra-flat and ultra-thin (20nm) epi-like Si enable across-layer and in-layer high-speed 3ps logic circuits and 1-T 500ns plasma-MONOS NVMs as well as 6T SRAMs with static noise margin (SNM) of 280 mV and reduced footprint by 25%. Closely stacked monolithic 3D circuits envision advanced high-performance, rich function, and low power intelligent mobile devices.

Record-high 121/62 μA/μm on-currents 3D stacked epi-like Si FETs with and without metal back gate

A sequential layered integration technology that can fabricate 3D stackable epi-like Si FETs with and without metal back gate (MBG) under sub-400°C are proposed in this article. With laser crystallized epi-like Si and CMP thinning processes for channel fabrication, 3D stackable ultra thin body (UTB) n/p-MOSFETs with low-subthreshold swings (88 and 121 mV/dec.) and high on-currents (121 and 62 μA/μm) are demonstrated. With additional metal back gate structure, UTB devices can be desirably operated in a positive or negative threshold voltage range with γ values of 0.51 (n-MOSFETs) and 0.56 (p-MOSFETs) for favoring its applications in 3D logic circuits. In addition, such thin and high quality channel and metal back gate scheme is not only promising for conventional p-n junction device but also junctionless (JL) scheme, which can simplify the fabrication and achieve further scaling.

Heterogeneously integrated sub-40nm low-power epi-like Ge/Si monolithic 3D-IC with stacked SiGeC ambient light harvester

For the first time, we report heterogeneously integrated sub-40nm epi-like Ge/Si monolithic 3D-IC with low-power logic/NVM circuits and efficient photovoltaic energy harvester. Threshold voltage engineering and driving current boosting technologies enable stackable Ge/Si UTB (<;15nm) MOSFETs, CMOS inverter and SRAM (SNM=270mV@0.7V) achieve low operation voltage. Stackable 1-T NVM with high speed (100ns) and low driving-voltage operation provide power-off storage while SRAM serve as power-on working memory. 100% aperture ratio SiGeC ambient light energy harvester with maximum output power of 7mW/cm2 layered on the monolithic 3D-IC chip envisions a self-powered monolithic 3D-IC technology for advanced low-power wire-less sensor networks, wearable devices, and devices for Internet of Things.

Low-cost and TSV-free monolithic 3D-IC with heterogeneous integration of logic, memory and sensor analogy circuitry for Internet of Things

For the first time, a CO2 far-infrared laser annealing (CO2-FIR-LA) technology was developed as the activation solution to enable highly heterogeneous integration without causing device degradation for TSV-free monolithic 3DIC. This process is capable to implement small-area-small-load vertical connectors, gate-first high-k/metal gate MOSFETs and non-Al metal inter-connects. Such a far-infrared laser annealing exhibits excellent selective activation capability that enables performance-enhanced stacked sub-40nm UTB-MOSFETs (Ion-enhanced over 50 %). Unlike TSV-based 3D-IC, this 3D Monolithic IC enables ultra-wide-IO connections between layers to achieve high bandwidth with less power consumption. A test chip with logic circuits, 6T SRAM, ReRAM, sense amplifiers, analog amplifiers and gas sensors was integrated to confirm the superiority in heterogeneous integration of proposed CO2-FIR-LA technology. This chip demonstrates the most variable functions above reported 3D Monolithic ICs. This CO2-FIR-LA based TSV-free 3D Monolithic IC can realize low cost, small footprint, and highly heterogeneous integration for Internet of Things.

Junction-less poly-Ge FinFET and charge-trap NVM fabricated by laser-enabled low thermal budget processes

A doping-free poly-Ge film as channel material was implemented by CVD-deposited nano-crystalline Ge and visible-light laser crystallization, which behaves as a p-type semiconductor, exhibiting holes concentration of 1.8 × 1018 cm−3 and high crystallinity (Raman FWHM ∼ 4.54 cm−1). The fabricated junctionless 7 nm-poly-Ge FinFET performs at an Ion/Ioff ratio over 105 and drain-induced barrier lowering of 168 mV/V. Moreover, the fast programming speed of 100 μs–1 ms and reliable retention can be obtained from the junctionless poly-Ge nonvolatile-memory. Such junctionless poly-Ge devices with low thermal budget are compatible with the conventional CMOS technology and are favorable for 3D sequential-layer integration and flexible electronics.

Fabrication of InGaP/Al/sub 0.98/Ga/sub 0.02/As/GaAs oxide-confined collector-up heterojunction bipolar transistors

A partially oxidized Al/sub 0.98/Ga/sub 0.02/As layer was introduced between the emitter and base of collector-up heterojunction bipolar transistors (C-up HBTs) to suppress the leakage current and improve the current gain. Dependence of device current gain and leakage current on oxidation temperature was investigated. At lower oxidation temperature, the current gain can be effectively improved. Current gain and base sheet resistance were 79 and 203 ohm/sq. for the C-up HBT oxidized at 400/spl deg/C.

Charge-trap non-volatile memories fabricated by laser-enabled low-thermal budget processes

We fabricated charge-trap non-volatile memories (NVMs) using low thermal budget processes, including laser-crystallization of poly-Si thin film, chemical vapor deposition deposition of a stacked memory layer, and far-infrared-laser dopant activation. The thin poly-Si channel has a low defect-density at the interface with the bulk, resulting in a steep subthreshold swing for the NVM transistors. The introduction of the stacked SiO2/AlOxNy tunnel layer and the SiNx charge-trap layer with a gradient bandgap leads to reliable retention and endurance at low voltage for the NVMs. The low thermal budget processes are desirable for the integration of the nano-scaled NVMs into system on panels.

V th adjustable self-aligned embedded source/drain Si/Ge nanowire FETs and dopant-free NVMs for 3D sequentially integrated circuit

3D stackable high-performance Si nanowire field-effect transistors (NWFETs) and dopant-free Ge junctionless nanowire non-volatile memories (JL-NWNVMs) with self-aligned embedded source/drain (S/D) current boosters and independent back gate (BG) V_th adjusters for 3D sequential integrated circuit are realized by low thermal budget process (<;450°C). The fabricated Si NWFETs exhibit low subthreshold swings (96 and 125 mV/dec.), high on-currents (232 and 110 μA/μm), and large γ value (>0.05) for V_th adjustment. The high-Δ capped blocking dielectric bandgap engineered dopant-free Ge JL-NWNVM exhibits high I_on/I_off ratio (>10⁵), large memory window (>4V), and low charge loss (<;40%, 10yrs). Thanks to the quantum confinement effect, such V_th adjustable nanowire devices perform well at higher temperatures, which give a wide design window for 3D sequential integrated circuit.

Enabling n-type polycrystalline Ge junctionless FinFET of low thermal budget by in situ doping of channel and visible pulsed laser annealing

A low-thermal-budget n-type polycrystalline Ge (poly-Ge) channel that was prepared by plasma in-situ-doped nanocrystalline Ge (nc-Ge) and visible pulsed laser annealing exhibits a high electrically active concentration of 2 × 1019 cm−3 and a narrow Raman FWHM of 3.9 cm−1. Furthermore, the fabricated n-type poly-Ge junctionless FinFET (JL-FinFET) shows an I on/I off ratio of 6 × 104, V th of −0.3 V, and a subthreshold swing of 237 mV/dec at V d of 1 V and DIBL of 101 mV/V. The poly-Ge JL-FinFET with a high-aspect-ratio fin channel is less sensitive to V th roll-off and subthreshold-swing degradation as the gate length is scaled down to 50 nm. This low-thermal-budget JL-FinFET can be integrated into three-dimensional sequential-layer integration and flexible electronics.

First fully functionalized monolithic 3D+ IoT chip with 0.5 V light-electricity power management, 6.8 GHz wireless-communication VCO, and 4-layer vertical ReRAM

For the first time, we report low-cost heterogeneously integrated sub-40nm epi-like Si monolithic internet of thins (IoT) 3D⁺-IC with wireless communication, light-electricity power management and vertical ReRAM (VRRAM) modules. High current driving multi-channel 3D⁺ UTB-MOSFETs (600μA/282μA@VG= ± 1V for 10-channel P/N FETs) was fabricated by low thermal budget super-CMP-planarized visible laser-crystallized epi-like Si channel and CO<inf>2</inf> far-infrared laser annealing (CO<inf>2</inf>-FIR-LA) activation technologies that support a 6.8GHz high frequency VCO circuits, 0.5V low-voltage power management circuit and drives 20nm 4-layer VRRAM (Set/Reset <1.2V/1.8V, 3-bits/cell). This unique TSV-free monolithic 3D⁺IC process provides the superiority in 3D hetero-integration; we successfully integrate these circuits in a low cost, small footprint, fully functionalized 3D⁺ IoT chip.