Chang-hyun Cho

Anomalous junction leakage current induced by STI dislocations and its impact on dynamic random access memory devices

As the density of dynamic random access memory (DRAM) increases up to giga-bit regime, one of the important problems is the control of the process-induced defects and damage. Although the shallow trench isolation (STI) is widely used for deep submicron devices, it has a great possibility of generating STI dislocations due to its inherently large mechanical stress and damage. When STI dislocations are located within the depletion region of pn junction, anomalous junction leakage current could flow. This junction leakage current degrades the memory cell data retention time and the standby current of DRAM. We resolved the problems from STI dislocations as follows; the crystal defects and the mechanical stress were reduced by optimizing the implantation condition and the densification temperature of trench filled high-density plasma (HDP) oxide, respectively. In addition, the residual mechanical stress before source/drain implantation was relieved through rapid thermal nitridation (RTN). By using these methods, STI dislocations were successfully clamped outside the depletion region of pn junction.

A BISR (built-in self-repair) circuit for embedded memory with multiple redundancies

This paper presents an efficient repair algorithm for embedded memory with multiple redundancies and a BISR (built-in self-repair) circuit using the proposed algorithm. While there are many repair algorithms which have good repair capability, their complexity is too high to implement. We present a repair algorithm which has good repair capability with little hardware overhead.

A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface

A monolithic 64 Gb MLC NAND flash based on 21 nm process technology has been developed. The device consists of 4-plane arrays and provides page size of up to 32 KB. It also features a newly developed asynchronous DDR interface that can support up to the maximum bandwidth of 400 MB/s. To improve performance and reliability, on-chip randomizer, soft data readout, and incremental bit line pre-charge scheme have been developed.

A 6F/sup 2/ DRAM technology in 60nm era for gigabit densities

A novel process technology for 6F/sup 2/ DRAM cell at 68nm design rule was for the first time developed. The cell size is 0.028/spl mu/m/sup 2/, which is the smallest cell size ever reported. ArF lithography with double expose technology and highly selective etching process were used for patterning of critical layers. This 6F cell was made of simple line/space patterns for easy patterning and self-aligned etches to improve process margins. MIM cell capacitor was developed with multi-layer high-k dielectric materials and 11A equivalent Tox and sub-lfA leakage was confirmed.

Robust memory cell capacitor using multi-stack storage node for high performance in 90 nm technology and beyond

90 nm DRAM technology and beyond requires the robust memory cell capacitor structure in order to increase cell capacitance for high performance and low power applications. Thus, the cell technology must have the feature of high capacitance of memory cell capacitor while maintaining its mechanical stability. To accomplish these purposes, we develop the multi-stack storage node structure whose enlarged bottom size of OCS(One Cylindrical Storage node) can give much better mechanical stability of the capacitor than that of the conventional capacitor. Using Al/sub 2/O/sub 3//HfO/sub 2/ dielectric material together with this structure can give high cell capacitance 30fF/cell and low leakage current less than 1fA/cell.

Chip-Level Simultaneous Switching Current Measurement in Power Distribution Network Using Magnetically Coupled Embedded Current Probing Structure

A simultaneous switching current (SSC) drawn by an integrated circuit (IC) creates simultaneous switching noise on power nets, which in turn causes jitters in the I/O signals and reduces the maximum clock frequency. For a thorough analysis of high-speed ICs, there is a dire need to measure currents at specific power pins of the ICs. In this paper, a novel magnetically coupled embedded current probing structure is proposed for measuring the SSC on the chip level resulting from the logical activity of the I/O buffers. SSCs are found by capturing the magnetic flux induced by the SSC of interest, with the proposed embedded current probing structure using magnetic coupling, and then reconstructing the original current waveform using the transfer impedance profile. Through a series of measurements with test vehicles fabricated on the chip level, we experimentally verified the proposed probing structures in the time and frequency domains and proved that they can effectively measure the SSC. Finally, future directions for improvements are discussed at the end of this paper.

Integrated device and process technology for sub-70nm low power DRAM

A novel process technology for 70nm DRAM was for the first time developed. ArF lithography with lithography friendly layout and highly selective etching process were used for patterning of critical layers. A novel gap-fill technology using spin coating oxide was used for STI and ILD processes. Metal tungsten on dual poly gate and dual gate oxide with plasma nitridation process was used for the performance of peripheral transistors. Bar type bit line contact was used to increase the transistor current about 10%. MIM cell capacitor was developed with buried-OCS scheme and 15/spl Aring/ equivalent Tox and 1fA leakage was confirmed.

70nm DRAM technology for DDR-3 application

For the first time, we developed 70nm DRAM technology applicable to a manufacturing level. This technology is aimed at DDR-3 application, which requires low-voltage operation and high speed performance. Fully working 70nm DRAMs were realized combining W-gate dual poly process, recess-channel-array-transistors (RCATs), and MIM cell capacitor module. In this paper, we present performance of 70nm node DRAMs which qualifies DDR-3 application requirement.

Free energy modeling of block-copolymer within pillar confinements on DSA lithography

To a major candidate and beyond, directed self-assembly (DSA) lithography is investigated on DRAM contact-hole fabrication. We perform a systematic study about behavior of asymmetric PS-b-PMMA block copolymers (BCP) within pillar confinement for DSA and find that selectively removed PMMA contact domain has a different morphology according to chemically modified pillar surfaces. We calculate the perturbation of PMMA contacts by pillar diameter using free energy magnitude model. This established model provides practical engineering insight for present pillar scheme and future graphoepitaxial self-assembly techniques for semiconductor DSA procedure.

Structural and Electrical Properties of Sol-gel Derived BFO/PZT Thin Films with Variation of Solvents

Multiferroic BFO/PZT(5/95) multilayer films were fabricated by spin-coating method on the Pt/Ti//Si substrate alternately using BFO and PZT(9/95) alkoxide solutions. The structural and dielectric properties were investigated with variation of the solvent and the number of coatings. All films showed the typical XRD patterns of the perovskite polycrystalline structure without presence of the second phase such as . BFO/PZT multilayer thin films showed the typical dielectric relaxation properties with increase an applied frequency. The average thickness of 6-coated BFO/PZT multilayer film was about 600 nm. The dielectric properties such as dielectric constant, dielectric loss and remnant polarization were superior to those of single composition BFO film, and those values for BFO/PZT multilayer film were 1199, 0.23% and 12 .