Hong-Sik Jeong

A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput

A 512Mb diode-switch PRAM is developed in a 90nm CMOS technology. A core configuration, read/write circuit techniques, and a charge-pump system for the diode-switch PRAM are described. Through these schemes, the PRAM achieves read throughput of 266MB/S and maximum write throughput of 4.64MB/S with a 1.8V supply.

A 0.1-

A 256-Mb phase-change random access memory has been developed, featuring 66-MHz synchronous burst-read operation. Using a charge pump system, write performance was characterized at a low supply voltage of 1.8 V. Measured initial read access time and burst-read access time are 62 and 10 ns, respectively. The write throughput was 0.5 MB/s with internal times2 write and can be increased to ~2.67 MB/s with times16 write. Endurance and retention characteristics are measured to be 107 cycles and ten years at 99 degC

\mu{\hbox {m}}

A non-volatile 64 Mb phase-transition RAM is developed by fully integrating a chalcogenide alloy GST (Ge/sub 2/Sb/sub 2/Te/sub 5/) into 0.18 /spl mu/m CMOS technology. This alloy is programmed by resistive heating. To optimize SET/RESET distribution, a 512 kb sub-core architecture, featuring meshed ground line, is proposed. Random read access and write access for SET/RESET are 60 ns, 120 ns and 50 ns, respectively, at 3.0 and 30/spl deg/C.

1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation

A 1.8 V 64 Mb phase-change RAM with improved write performance is fabricated in a 0.12 /spl mu/m CMOS technology. The improvement of RESET and SET distributions is based on cell current regulation and multiple step-down pulse generators. The read access time and SET-write time are 68 ns and 180 ns respectively.

A 0.18 /spl mu/m 3.0 V 64 Mb non-volatile phase-transition random-access memory (PRAM)

We observed the atomic structures for each reset and set state in a phase-change random access memory fabricated using stoichiometric crystalline Ge 2 Sb 2 Te 5 . The reset state clearly showed a mixture of dome-shaped amorphous and crystal structure surrounding amorphous, but the set state showed abnormally grown large grains due to recrystallization of the amorphous structure. The crystal structure of the recrystallized grain was face-centered cubic. The element analysis indicated that the atomic composition changes to nonstoichiometric phase in the active regions of the reset and the set state, which is Sb-rich and Te-deficient compared to the pristine stoichiometric composition. Analysis showed that thermal interdiffusion of Sb and Te caused nonstoichiometric nature of the material to reach the energetically stable state in the active region.

Enhanced write performance of a 64 Mb phase-change random access memory

Phase-change random access memory is considered a potential challenger for conventional memories, such as dynamic random access memory and flash memory due to its numerous advantages. Nevertheless, high reset current is the ultimate problem in developing high-density phase-change random access memory (PRAM). We focus on the adoption of Ge2Sb2Te5 confined structures to achieve lower reset currents. By changing from a normal to a GST confined structure, the reset current drops to as low as 0.8 mA. Eventually, our integrated 64 Mb PRAM based on 0.18 µm CMOS technology offers a large sensing margin: Rreset ~200 kΩ and Rset ~2 kΩ, as well as reasonable reliability: an endurance of 1.0×109 cycles and a retention time of 2 years at 85°C.

Phase-Change Behavior of Stoichiometric Ge2Sb2Te5 in Phase-Change Random Access Memory

A nonvolatile 16-kb one-transistor one-magnetic-tunnel-junction (1T1MTJ) magnetoresistance random access memory with 0.24-/spl mu/m design rules was developed by using a self-reference sensing scheme for reliable sensing margin. This self-reference sensing scheme was achieved by first storing a voltage of the magnetic tunnel junction (MTJ), and then after a time interval storing a reference voltage of the same MTJ (self-reference). The effects of variation in tunneling oxide thickness can be eliminated by this self-reference sensing scheme. As a result, reliable sensing of MRAM devices with MTJ resistance of 2.5-11 k/spl Omega/ was achieved.

Ge2Sb2Te5 Confined Structures and Integration of 64 Mb Phase-Change Random Access Memory

A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-/spl mu/m CMOS process. The large density of integration and severe device fluctuation present challenges in dealing with the on-chip skews, packaging, and processing technology. Circuit techniques and schemes of outer DQ and inner control (ODIC) chip with a non-ODIC package, cycle-time-adaptive wave pipelining, and variable-stage analog delay-locked loop with the three-input phase detector can provide precise skew controls and increased tolerance to processing variations. DDR as a viable high-speed and low-voltage DRAM I/O interface is demonstrated.

A 0.24-/spl mu/m 2.0-V 1T1MTJ 16-kb nonvolatile magnetoresistance RAM with self-reference sensing scheme

An advanced bottom electrode contact (BEC) was successfully developed for reliable high-density 256 Mb phase-change random access memory (PRAM) using a ring-type contact scheme. This advanced ring-type BEC was prepared by depositing very thin TiN films inside a contact hole, after which core dielectrics were uniformly filled into the TiN-deposited contact hole. Using this novel contact scheme, it was possible to reduce reset current while maintaining a low set resistance and a uniform cell distribution. Thus, it has been clearly demonstrated that the use of the ring-type contact technology is very feasible for high-density PRAM beyond 256 Mb.

A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM

As mobile appliances are prevailing in our daily lives, the nonvolatile memory suitable for mobile applications becomes indispensable elements and it is anticipated that the nonvolatile memory usage is much increased in future due to much diversified applications. Therefore it is very appropriate and important to look into where the nonvolatile memory technologies are now, what the challenges are, and where the future technologies should go. In this study, two major devices of nonvolatile memory i.e., NAND flash and NOR flash are reviewed and then the newly emerging nonvolatile memory i.e., PRAM (phase change memory), and FRAM (ferroelectric memory) are discussed.