Chang-Jin Jeong

An Integrated High-Performance Active Rectifier for Piezoelectric Vibration Energy Harvesting Systems

In this letter, a highly efficient active full-bridge rectifier is proposed for piezoelectric (PE) vibration energy harvesting systems. By replacing the passive diodes with an operational amplifier-controlled active counterpart and adding a switch in parallel with the transducer, the proposed rectifier solves the dc-offset problem of the comparator-based active diode, minimizes the voltage drop along the conduction path, and extracts more power from the transducer, all of which lead to better power extraction and conversion capability. The proposed rectifier, implemented in 0.18-μm CMOS technology, shows 90% power conversion efficiency and 81 μW output power, with values corresponding to 1.5 times and 3.4 times the values for a conventional full-bridge rectifier.

A New Approach to Low-Power and Low-Latency Wake-Up Receiver System for Wireless Sensor Nodes

A new wake-up receiver is proposed to reduce energy consumption and latency through adoption of two different data rates for the transmission of wake-up packets. To reduce the energy consumption, the start frame bits (SFBs) of a wake-up packet are transmitted at a low data rate of 1 kbps, and a bit-level duty cycle is employed for detection of SFBs. To reduce both energy consumption and latency, duty cycling is halted upon detection of the SFB sequence, and the rest of the wake-up packet is transmitted at a higher data rate of 200 kbps. The proposed wake-up receiver is designed and fabricated in a 0.18 μm CMOS technology with a core size of 1850×1560 μm for the target frequency range of 902-928 MHz. The measured results show that the proposed design achieves a sensitivity of -73 dBm, while dissipating an average power of 8.5 μW from a 1.8 V supply.

A 50-300-MHz low power and high linear active RF tracking filter for digital TV tuner ICs

A low power and highly linear CMOS active tracking bandpass filter is presented to overcome a local oscillator harmonic mixing problem for Digital TV tuner ICs. A transconductor linearization technique based on a method of dynamic source degenerated differential pair is adopted to improve the linearity performance. The newly proposed low power high quality factor (Q) biquad and the linearized transconductor with negative resistance load (NRL) enables a low power and high Q RF tracking filter design. The total chip area is 0.25 mm X 0.9 mm. The fabricated tracking filter based on the 0.13 um CMOS process shows 48∼300 MHz tracking range with 10∼50 MHz bandwidth, more than 38 dB 3rd order harmonic rejection, 6 dB unwanted signal rejection@N+6 channel offset, and a maximum IIP3 of 6 dBm at 5 dB gain while drawing 6.4 mA from a 1.2 V supply.

A high efficiency piezoelectric energy harvesting system

Nowadays, harvested energy from surrounding environment plays an important role in the human life. This green energy gradually replaced for traditional energy such as fossil energy. Several methods have been used to capture green energy from environmental source. One of the most popular method is using piezoelectric material to harvest energy from vibration source. A piezoelectric energy harvesting system include two sections: a transducer to convert potential energy to the electrical energy and an electrical interface to manage this energy. Normally, a rectifier and voltage regulator are two main components in the electrical interface. In this paper, a new high efficiency piezoelectric energy harvesting system is proposed to increase extracted power from piezoelectric. By using two synchronized switches, the extracted efficiency of the rectifier is double. Furthermore, the passive diode of the conventional rectifier is replaced by active diode to increase the conversion efficiency of rectifier. The simulation result show that the power extraction efficiency of the rectifier is 3.5 times that of the conventional full bride rectifier, and more than 93% of power conversion efficiency can be achieved. To completely piezoelectric energy harvesting system a Low-drop regulator (LDO) is used to regulate voltage at the output of rectifier. The LDO gets maximum 90% efficiency with 3mV voltage ripple. The overall efficiency of proposed system gets 83.3%.

A 1.5V, 140µA CMOS ultra-low power common-gate LNA

This paper presents design guidelines for ultra-low power Low Noise Amplifier (LNA) design by comparing input matching, gain, and noise figure (NF) characteristics of common-source (CS) and common-gate (CG) topologies. A current-reused ultra-low power 2.2 GHz CG LNA is proposed and implemented based on 0.18 um CMOS technology. Measurement results show 13.9 dB power gain, 5.14 dB NF, and −9.3 dBm IIP3, respectively, while dissipating 140 uA from a 1.5 V supply, which shows best figure of merit (FOM) among all published ultra-low power LNAs.

A high speed comparator based active rectifier for wireless power transfer systems

Wireless power transfer technique can be used in many applications nowadays. The main limitation of this wireless power transfer system is in their interface circuitry. In this paper, a highly efficient active rectifier is proposed. By adopting the high speed comparator and, proposed rectifier solved the turn on and off delay of power transistor problem of conventional rectifier and shows high power conversion efficiency. Based on 0.35 um CMOS technology, the simulated power efficiency of the proposed rectifier is 92%. The proposed active rectifier improves upon the power conversion efficiency by 1.66 times compared to the conventional one.

A 2.2 mW, 40 dB Automatic Gain Controllable Low Noise Amplifier for FM Receiver

This paper presents an automatic gain controllable low noise amplifier (AGC-LNA) for FM receiver (FMRx). The proposed LNA adopts current reused dual gm-boosting technique for the power saving. And, a simple analog type automatic gain control (AGC) loop is proposed that provides high resolution gain control. Implemented in a 65 nm CMOS technology, measurements show power regulation range of 40 dB with ±1 dB error, less than -11 dB of S11, variable voltage gain range of -12 to 30 dB over the frequency range of 88 ~ 108 MHz, noise figure (NF) of less than 2.9 dB, P1dB of higher than -24.2 dBm, and IIP3 of higher than -12.7 dBm in the high gain (HG) mode, while dissipating only 1.8 mA from a 1.2 V supply, respectively.

A high linear low flicker noise 25% duty cycle LO I/Q mixer for a FM radio receiver

In this paper, a low power, low flicker noise and high IIP3 I/Q mixer for 76–108MHz EURO/US/Korea/Japan FM radio receiver applications is presented. The proposed mixer includes a transconductance (Gm) stage, a current mode passive switching stage driven by a 25% duty cycle LO, a transimpedance amplifier (TIA), and a 25% duty cycle LO generator. Simulation results show a 9.2dB DSB noise figure at 50kHz, 13dBm IIP3, and 23dB voltage gain, respectively, while drawing only 800uA including a LO generator from a 1.2-V supply in a standard 65nm CMOS technology.

A fully integrted RSSI with wide dynamic range, low power consumption in DVB-H.

In this paper, a low power, wide dynamic range RSSI circuit which adopts output to output feedback for DC offset cancellation is presented.