Sok-Kyun Han

A 1.5V, 140µA CMOS ultra-low power common-gate LNA

This paper presents design guidelines for ultra-low power Low Noise Amplifier (LNA) design by comparing input matching, gain, and noise figure (NF) characteristics of common-source (CS) and common-gate (CG) topologies. A current-reused ultra-low power 2.2 GHz CG LNA is proposed and implemented based on 0.18 um CMOS technology. Measurement results show 13.9 dB power gain, 5.14 dB NF, and −9.3 dBm IIP3, respectively, while dissipating 140 uA from a 1.5 V supply, which shows best figure of merit (FOM) among all published ultra-low power LNAs.

Low power high linearity transmitter front-end for 900 MHz Zigbee applications

This paper presents a low power high linearity transmitter front-end for 900 MHz Zigbee applications based on 0.18 mum CMOS technology. The direct up-conversion is implemented by passive mixer which dissipates no DC current. Two stage driver amplifiers provide high enough gain as well as high linearity to drive high power signal to 50Omega antenna while consuming small amount of current. Measurement shows 11.5 dB overall transmitter gain, 3 dBm output P1dB while dissipating 1.8mA DC current from 1.8 V supply

Load-Balance-Independent High Efficiency Single-Inductor Multiple-Output (SIMO) DC-DC Converters

A single-inductor multiple-output (SIMO) DC-DC converter providing buck and boost outputs with a new switching sequence is presented. In the proposed switching sequence, which does not require any additional blocks, input energy is delivered to outputs continuously by flowing current through the inductor, which leads to high conversion efficiency regardless of the balance between the buck and boost output loads. Furthermore, instead of multiple output loop compensation, only the freewheeling current feedback loop is compensated, which minimizes the number of off-chip components and nullifies the need for the equivalent series resistance (ESR) of the output capacitor for loop compensation. Therefore, power conversion efficiency and output voltage ripples can be improved and minimized, respectively. Implemented in a 0.35- μm CMOS, the proposed SIMO DC-DC converter achieves high conversion efficiency regardless of the load balance between the two outputs with maximum efficiency reaching up to 82% under heavy loads.

Low power high linearity driver amplifier for 900 MHz Zigbee applications

This paper presents a low power high linearity driver amplifier for 900 MHz Zigbee applications based on 0.18 /spl mu/m CMOS technology. In this work folded cascode amplifier is adopted to get more efficient power transmission. High gain and linearity are achieved by applying resonating load and gain boosting technique. Measurements show 11.5 dB gain, 3 dBm output P1dB while dissipating 1.8mA DC current from 1.8 V supply.

A 200-V 98.16%-Efficiency Buck LED Driver Using Integrated Current Control to Improve Current Accuracy for Large-Scale Single-String LED Backlighting Applications

This paper presents an average current mode buck dimmable light-emitting diode (LED) driver for large-scale single-string LED backlighting applications. The proposed integrated current control technique can provide exact current control signals by using an autozeroed integrator to enhance the accuracy of the average current of LEDs while driving a large number of LEDs. Adoption of discontinuous low-side current sensing leads to power loss reduction. Adoption of a fast-settling technique allows the LED driver to enter into the steady state within three switching cycles after the dimming signal is triggered. Implemented in a 0.35-μm HV CMOS process, the proposed LED driver achieves 1.7% LED current error and 98.16% peak efficiency over an input voltage range of 110 to 200 V while driving 30 to 50 LEDs.

A Fast Low Dropout Regulator with High Slew Rate and Large Unity-Gain Bandwidth

A low dropout regulator (LDO) with fast transient responses is presented. The proposed LDO eliminates the trade-off between slew rate and unity gain bandwidth, which are the key parameters for fast transient responses. In the proposed buffer, by changing the slew current path, the slew rate and unity gain bandwidth can be controlled independently. Implemented in 0.18- ㎛ high voltage CMOS, the proposed LDO shows up to 200 ㎃ load current with 0.2V dropout voltage for 1㎌ output capacitance. The measured maximum transient output voltage variation, minimum quiescent current at no load condition, and maximum unity gain frequency are 24 ㎷, 7.5㎂, and higher than 1 ㎒, respectively.

A 64 µW, 23 dB gain, 8 dB NF, 2.4 GHz RF front-end for ultra-low power Internet-of-Things transceivers

An ultra-low power (ULP) 2.4 GHz RF front-end which consists of a low noise amplifier (LNA) and a passive mixer in a standard 65nm CMOS is presented. LNA adopts a complementary input stage and a current reused 2nd gain stage to achieve a high gain under a low power dissipation with an added linearization method. RF Down-conversion is implemented with a highly linearized complementary passive mixer, which adopts transmission gate type switches. With fully on-chip components, the front-end achieves 23 dB conversion gain, 8 dB NF, −36 dBm P1dB and −21 dBm IIP3 while dissipating a 64 µW power from a 0.6 V supply voltage. LNA achieves a high voltage gain of 26.3 dB and minimum NF of 5.5 dB with a P1dB of −27 dBm and IIP3 of −13 dBm.

A 900-mV Area-Efficient Source-Degenerated CMOS Four-Quadrant Multiplier with 10.6-GHz Bandwidth

This paper presents a low-voltage area-efficient four-quadrant CMOS multiplier reconfigured in a sourcedegenerated topology and designed as a part of a correlator for an integrated ultra-wideband (UWB) transceiver. The simulation based on a 0.18-µm CMOS technology shows that the multiplier offers 10.6-GHz bandwidth while dissipating 290 µA from a 0.9- V supply.