Jun-Sik Yoon

Patterned growth of single-walled carbon nanotube arrays from a vapor-deposited Fe catalyst

Single-walled carbon nanotubes have been grown on a variety of substrates by chemical vapor deposition using low-coverage vacuum-deposited iron as a catalyst. Ordered arrays of suspended nanotubes ranging from submicron to several micron lengths have been obtained on Si, SiO 2 , Al 2 O 3 , and Si 3 N 4 substrates that were patterned on hundred nanometer length scales with a focused ion beam machine. Electric fields applied during nanotube growth allow the control of growth direction. Nanotube circuits have been constructed directly on contacting metal electrodes of Pt/Cr patterned with catalysts. Patterning with solid iron catalyst is compatible with modern semiconductor fabrication strategies and may contribute to the integration of nanotubes in complex device architectures.

Size-dependent impurity activation energy in GaN nanowires

The effect of the surrounding dielectric on the conductivity of GaN nanowires is measured experimentally. The two following configurations are considered: bare suspended and SiO2-coated nanowires. The measured conductivity is consistently fitted by two exponential terms with different activation energies, indicating multichannel conduction. The larger energy, attributed to activation of impurities into the conduction subband, shows essentially inverse dependence on nanowire radius, consistent with the dielectric confinement effect. This agrees with calculated values from finite element analysis. The smaller energy is independent of the nanowire radius, suggesting a surface conduction channel.

Investigation of Low-Frequency Noise Behavior After Hot-Carrier Stress in an n-Channel Junctionless Nanowire MOSFET

The dc performance and low-frequency (LF) noise behaviors after hot-carrier (HC)-induced stress were compared for a junctionless nanowire transistor (JNT) and an inversion-mode nanowire transistor (INT). Less dc degradation was found in the JNT than in the INT. Due to the low lateral peak electric field (E-field) and electrons traveling through the center of the nanowire, the LF noise increment after HC-induced stress in the JNT is much lower than that in the INT. Furthermore, due to the higher lateral peak E-field located under the gate and the conduction path that occurs near the surface, the LF noise of the INT is very sensitive to HC stress.

Statistical variability study of random dopant fluctuation on gate-all-around inversion-mode silicon nanowire field-effect transistors

Random dopant fluctuation effects of gate-all-around inversion-mode silicon nanowire field-effect transistors (FETs) with different diameters and extension lengths are investigated. The nanowire FETs with smaller diameter and longer extension length reduce average values and variations of subthreshold swing and drain-induced barrier lowering, thus improving short channel immunity. Relative variations of the drain currents increase as the diameter decreases because of decreased current drivability from narrower channel cross-sections. Absolute variations of the drain currents decrease critically as the extension length increases due to decreasing the number of arsenic dopants penetrating into the channel region. To understand variability origins of the drain currents, variations of source/drain series resistance and low-field mobility are investigated. All these two parameters affect the variations of the drain currents concurrently. The nanowire FETs having extension lengths sufficient to prevent dopant p...

Vertical gate-all-around junctionless nanowire transistors with asymmetric diameters and underlap lengths

Vertical gate-all-around (GAA) junctionless nanowire transistors (JNTs) with different diameters and underlap lengths are investigated using three-dimensional device simulations. The source-side diameter determines the on-current and drain-induced barrier lowering characteristics, whereas the drain-side diameter controls the band-to-band tunneling current during off-state conditions. The JNTs with short drain-side underlap lengths decrease the source/drain series resistance but increase the off-current values, especially due to large band-gap narrowing effects at the drain extension region. Proper device design of vertical GAA JNTs considering the device structure and underlap is needed to improve both on/off and short channel characteristics.

Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node

DC/AC characteristics of Si bulk FinFETs including middle-of-line levels are precisely investigated using well-calibrated 3-D device simulations for system-on-chip applications. Scaling the fin widths down to 5 nm effectively enhances gate-to-channel controllability and improves RC delay, but a dramatic increase in band-to-band tunneling currents from source-to-drain does not satisfy low-power application in the 7-nm node. All lightly-doped extension regions as a solution could improve band-to-band tunneling currents and total gate capacitances because of better short-channel immunity and lower parasitic capacitances, respectively. Using systematic TCAD-based RC calculation, we suggest optimized overlap/underlap lengths in the 7-nm node FinFETs to overcome the scaling limitations.

Electrical Characteristics of Doped Silicon Nanowire Channel Field-Effect Transistor Biosensors

Optimization of operation conditions for biosensing is investigated for the doped silicon nanowire channel transistor sensors. Sensors with phosphorus doped honeycomb nanowire channel are fabricated on 8-in wafer using the conventional CMOS technology. From the low frequency noise characteristics, the noise equivalent gate voltage fluctuation is obtained to evaluate the sensor resolution and optimize the operation condition. The sensor exhibits maximum resolution at the flat band voltage condition. Detection of a neurotransmitter, dopamine, is demonstrated using the fabricated devices, showing a detection limit of 1 fM and a sensitivity of 2.3 mV/log[dopamine] with a resolution of ~60 levels/log[dopamine].

Process-Induced Variations of 10-nm Node Bulk nFinFETs Considering Middle-of-Line Parasitics

Process-induced variations of 10-nm node n-type FinFETs considering middle-of-line parasitics were investigated in terms of dc/ac performances using fully calibrated TCAD simulations. Variations of positive fixed oxide charge density at shallow trench isolation interface and source/drain (S/D) height influenced off-state and on-state performance variations, respectively, but slightly on RC delay variations. Fin width variations induced off-state performance and RC delay variations critically due to the fluctuation of short channel effects. But, fin height variations affected them slightly due to the preserved gate-to-channel controllability and the buffered effects by varying drain currents and gate capacitances in the same direction. Gate length, spacer length, and S/D length variations influenced dc/ac performance variations severely; 2-nm-length changes were barely acceptable to satisfy 10% RC delay margin. Thus, the process-induced variability parameters, including fin width, gate length, spacer length, and S/D length, should be controlled tightly under a few nanometers to reduce dc/ac performance variations of the FinFETs.

Variability study of Si nanowire FETs with different junction gradients

Random dopant fluctuation effects of gate-all-around Si nanowire field-effect transistors (FETs) are investigated in terms of different diameters and junction gradients. The nanowire FETs with smaller diameters or shorter junction gradients increase relative variations of the drain currents and the mismatch of the drain currents between source-drain and drain-source bias change in the saturation regime. Smaller diameters decreased current drivability critically compared to standard deviations of the drain currents, thus inducing greater relative variations of the drain currents. Shorter junction gradients form high potential barriers in the source-side lightly-doped extension regions at on-state, which determines the magnitude of the drain currents and fluctuates the drain currents greatly under thermionic-emission mechanism. On the other hand, longer junction gradients affect lateral field to fluctuate the drain currents greatly. These physical phenomena coincide with correlations of the variations betwe...

Impact of the spacer dielectric constant on parasitic RC and design guidelines to optimize DC/AC performance in 10-nm-node Si-nanowire FETs

In this paper, we propose an optimized design for Si-nanowire FETs in terms of spacer dielectric constant (κsp), extension length (LEXT), nanowire diameter (Dnw), and operation voltage (VDD) for the sub-10 nm technology node. Using well-calibrated TCAD simulations and analytic RC models, we have quantitatively evaluated geometry-dependent parasitic series resistances (RSD) and capacitances (Cpara). Compared with low-κ spacers, high-κ spacers exhibit a higher on/off-current ratio with a lower RSD, but show severe degradation in their AC performance owing to a higher Cpara. Considering the trade-off between RSD and Cpara, optimal geometry-dependent κsp values at various supply voltages (VDD) are determined using gate delay (CV/I) and current-gain cutoff frequency (fT). We found that as LEXT and VDD decrease and Dnw increases, the optimal κsp value shifts from the high-κ to low-κ regime.