Bomsoo Kim

Edge Profile Effect of Tunnel Oxide on Erase Threshold-Voltage Distributions in Flash Memory Cells

The erase threshold-voltage (VT) distribution in Flash electrically erasable programmable read-only memory cells was investigated versus the tunnel oxide edge profiles in self-aligned shallow trench isolation (SA-STI) and self-aligned poly (SAP) cells. The capacitive coupling with offset voltage correction is transcribed into VT transient for simulating erase VT dispersion without numerous full structure device simulations. It is shown that SAP gives rise to smaller VT dispersion, compared with SA-STI. The VT dispersion resulting from variations in dielectric thickness and oxide edge profiles is shown to fall far short of observed VT distribution, calling for examination of additional process and cell parameters

Reliable extraction of cycling induced interface states implementing realistic P/E stresses in reference cell: comparison with flash memory cell

The cycling induced interface states in floating-gate EEPROM cells are reliably extracted by implementing accurate program/erase stresses in the reference cell. The interface states measured directly from the memory cell via charge pumping are shown different from those obtained conventionally from the reference cell. The reasons for these different levels of extraction are elucidated and a new method is presented for accurate determination of interface trap density. The technique is based on introducing the equivalent gate voltage with offset voltage at the reference cell by which to simulate realistically the cycling stresses as occur in the flash memory cell itself.

Silicon Nanowire Field-Effect Transistor

The field effect transistor was conceived in 1930s and was demonstrated in 1960s. Since then, MOSFET emerged as the mainstream driver for the digital information technology. Because of the simplicity of structure and low cost of fabrication, it lends to a large scale integration for the multifunctional system-on-chip (SOC) applications. Moreover, the device has been relentlessly downsized for higher performance and integration. The physical barriers involved in downscaling the device have prompted the development of process technologies. There has also been the development of device structures from 3D bulk to the gate-all-around nanowire. This chapter is addressed to the discussion of the silicon nanowire field effect transistor (SNWFET). The discussion is carried out in comparison and correlation with the well known theory of MOSFET. The similarities and differences between the two FETs are highlighted, thereby bringing out features unique to SNWFET. Also, an emphasis is placed upon the underlying device physics rather than the device modeling per se. The goal of this chapter is to provide a background by which to comprehend the theories being developed rapidly for SNWFETs.

Three-Dimensional Simulation of Dopant-Fluctuation-Induced Threshold Voltage Dispersion in Nonplanar MOS Structures Targeting Flash EEPROM Transistors

Threshold voltage dispersion due to random discrete dopant fluctuation was simulated in recessed-channel, triple-gate, and saddle MOS structures, targeting future floating-gate memory cell transistor. All nonplanar structures showed improved dispersion characteristics, compared with the planar type by proper adjustment of the tunnel oxide structure and channel doping level. The recessed-channel showed a continuous improvement of dispersion with the channel area widening beyond a certain threshold recess depth. In triple-gate structure, a significant reduction in dispersion is shown possible primarily via the superior gate controllability. Among the nonplanar structures, the saddle structure yielded the lowest variation for a fixed target with the choice of moderate device parameters from the other structures.

Highly Reliable 256Mb NOR Flash MLC with Self-Aligned Process and Controlled Edge Profile

We present a comparative investigation of two self-aligned processes, viz. Self-Aligned Poly (SAP) and Self-Aligned STI (SA-STI) for high-density flash memory cells. SAP is shown to lead to narrow erase Vth dispersion and better endurance reliability via the control of oxide edge profile. The erase Vth dispersion is systematically simulated vs. process variations, confirming the sensitive role of edge profile in affecting F-N tunneling current. We also present a successful operation of 256Mb NOR flash MLC, fabricated with a 90 nm technology by SAP process.

Simple Experimental Determination of the Spread of Trapped Hot Holes Injected in Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) Cells: Optimized Erase and Cell Shrinkage

In this paper, we present a simple experimental method to extract the effective length of trapped holes in the nitride resulting from the hot hole injection (HHI) in Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory cells. The method utilizes the correlation between the threshold voltage (VTH) lowering and dispersion by HHI and the VTH roll-off in virgin samples. We also interpret the observed program/erase endurance cycling in light of HHI results, and find the minimum erasing time for maintaining the endurance margin for given device. Finally, we discuss the channel length scaling issues in SONOS cells, using HHI erase, cycling and off current data.

Spatial and Temporal Characterization of Programming Charge in SONOS Memory Cell: Effects of Localized Electron Trapping

Unique features of the threshold voltage shift, ΔVTH and the source current, IS in SONOS cells are quantified, utilizing the concept of trapped and localized electron charge, QT. Dependence of ΔVTH on forward and reverse readings, and on drain or source voltages are systematically analyzed for a given programming condition. Also constant transient IS during the programming is elucidated. The analysis is based upon embedding localized QT in, and solving the coupled Poisson and continuity equations. As a consequence, QT profiles diffusing progressively in time into the channel from its drain end is quantified. The technique for extracting the trap density and studying the cell reliability has been developed.

Correction to “Edge Profile Effect of Tunnel Oxide on Erase Threshold Voltage Distributions in Flash Memory Cells”

In the original article by B. Kim (see ibid., vol. 53, no. 12, p. 3012-3019, Dec. 2006) the biography for Dr. Kinam Kim was out of date. A more current one is given.

Characterization of near-interface oxide trap density in remote plasma nitrided oxides for nano-scale MOSFETs

Presented in this paper is the extracted depth profile of oxide trap density in ultra thin remote plasma nitrided oxides (RPNO) using multi-frequency and temperature charge pumping (CP) technique. The optimum nitrogen concentration in RPNO is discussed versus the gate oxide thickness for nano-scale CMOSFET.

Design Technique for Ramped Gate Soft-Programming in Over-Erased NOR Type Flash EEPROM Cells

We present an efficient design technique for implementing the optimal ramped gate soft-programming for curing the over-erased flash EEPROM cells. The technique does not rely on any I–V model but is solely based upon using the actual cell performance data and enables accurate prediction of programming time, given supply current (IS). The full utilization of available supply current renders the programming speed much faster and also enables reliable multi-bit soft-programming. The ramped gate scheme induces a strong self-convergence of the simultaneously up-shifted threshold voltages regardless of their initial values or the variations of the shift speed from cell to cell.