Kangmin Hu

A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS

A single-channel, asynchronous successive-approximation (SA) ADC with improved feedback delay is fabricated in 40 nm CMOS. Compared with a conventional SAR structure that employs a single quantizer controlled by a digital feedback logic loop, the proposed SAR-ADC employs multiple quantizers for each conversion bit, clocked by an asynchronous ripple clock that is generated after each quantization. Hence, the sampling rate of the 6-bit ADC is limited only by the six delays of the Capacitive-DAC settling and each comparators quantization delay, as the digital logic delay is eliminated. Measurement results of the 40 nm-CMOS SAR-ADC achieves a peak SNDR of 32.9 dB and 30.5 dB, at 1 GS/s and 1.25 GS/s, consuming 5.28 mW and 6.08 mW, leading to a FoM of 148 fJ/conv-step and 178 fJ/conv-step, respectively, in a core area less than 170 um by 85 um.

A 0.6 mW/Gb/s, 6.4–7.2 Gb/s Serial Link Receiver Using Local Injection-Locked Ring Oscillators in 90 nm CMOS

This paper describes a quad-lane, 6.4-7.2 Gb/s serial link receiver prototype using a forwarded clock architecture. A novel phase deskew scheme using injection-locked ring oscillators (ILRO) is proposed that achieves greater than one UI of phase shift for multiple clock phases, eliminating phase rotation and interpolation required in conventional architectures. Each receiver, optimized for power efficiency, consists of a low-power linear equalizer, four offset-cancelled quantizers for 1:4 demultiplexing, and an injection-locked ring oscillator coupled to a low-voltage swing, global clock distribution. Measurement results show a 6.4-7.2 Gb/s data rate with BER < 10-12 across 14 cm of PCB, and also an 8.0 Gb/s data rate through 4 cm of PCB. Designed in a 1.2 V, 90 nm CMOS process, the ILRO achieves a wide tuning range from 1.6-2.6 GHz. The total area of each receiver is 0.0174 mm2, resulting in a measured power efficiency of 0.6 mW/Gb/s.

A 90 nm-CMOS, 500 Mbps, 3–5 GHz Fully-Integrated IR-UWB Transceiver With Multipath Equalization Using Pulse Injection-Locking for Receiver Phase Synchronization

A fully-integrated, 3-5 GHz Impulse-Radio UWB transceiver with on-chip flash ADC is designed in 90 nm-CMOS. A new scheme for receiver phase acquisition is proposed that uses pulse injection-locking to synchronize the receive clock with the transmitted data, eliminating the need for clock/data recovery (CDR), requiring only static receiver phase alignment with the transmitted pulses at startup. Transmitter pre-emphasis equalization is utilized to mitigate the effect of multipath on bit-error rate (BER). Occupying 2 mm2 die area, the transceiver achieves a data rate of 500 Mbps, energy efficiency of 0.18 nj/b at 500 Mbps, and a RX raw BER of <; 10-3 across a distance of 10 cm at 125 Mbps. In a real multipath environment, BER improves by 2.35× after equalization of the first multipath reflection.

Receiver jitter tracking characteristics in high-speed source synchronous links

High-speed links which employ source synchronous clocking architectures have the ability to track correlated jitter between clock and data channels up to high frequencies. However, system timing margins are degraded by channel skew between clock and data signals and high-frequency loss. This paper describes how these key channel effects impact the jitter performance and influence the clocking architecture of high-speed source synchronous links. Tradeoffs in complexity and jitter tracking performance of common per-channel de-skew circuits are discussed, along with how band-pass filtering can be leveraged to provide additional jitter filtering at the receiver. Jitter tolerance analysis for a 10Gb/s system shows that a near all-pass delay-locked loop (DLL) and phase-interpolator- (PI-) based de-skew performs best under low skew conditions, while, at high skew, architectures which leverage band-pass clock filtering or a phase-locked loop (PLL) for increased jitter filtering are more suitable. De-skew based on injection-locked oscillators (ILOs) offer a reduced complexity design and competitive jitter tolerance over a wide skew range.

0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking

A near-threshold forwarded-clock I/O receiver architecture is presented. In the proposed receiver, the majority of the circuitry is designed to operate in the near-threshold region at 0.6 V supply to save power, with the exception of only the global clock buffer, test buffers and synthesized digital circuits at the nominal 1 V supply. To ensure the quantizers are working properly with this low supply, a 1:10 direct demultiplexing rate is chosen as a demonstration of achieving low supply operation by high-parallelism. A novel low-power super-harmonic injection-locked ring oscillator is proposed to generate deskewable symmetric multi-phase local clock phases. The relative performance impact of including a per-data lane sample-and-hold (S/H) to improve quantizer aperture time at low voltage is demonstrated with two receiver prototypes fabricated in a 65 nm CMOS technology. Including the amortized power of global clock distribution, the receiver without S/H consumes 1.3 mW and the one with S/H consumes 2 mW at an 8 Gb/s input data rate, which converts to 0.163 pJ/bit and 0.25 pJ/bit, respectively. Measurement results show both receivers get BER <; 10-12 across a 20-cm FR4 PCB channel.

A 90nm-CMOS, 500Mbps, fully-integrated IR-UWB transceiver using pulse injection-locking for receiver phase synchronization

A fully-integrated, 3.1–5GHz Impulse-Radio UWB transceiver with on-chip flash ADC is designed in 90nm-CMOS. A new scheme for receiver phase acquisition is proposed that uses pulse injection-locking to synchronize the receive clock with the transmitted data, eliminating the need for clock/data recovery (CDR). Occupying 2mm2 die area, the transceiver achieves a maximum data rate of 500 Mbps, energy efficiency of 0.18nJ/b at 500Mbps, and a RX-BER of 10−3 across a distance of 10cm at 125Mbps.

A Comparative Study of 20-Gb/s NRZ and Duobinary Signaling Using Statistical Analysis

A statistical analysis technique for estimating bit-error rate (BER) and eye opening is presented for both non-return-to-zero (NRZ) and duobinary signaling schemes. This method enables fast and accurate BER distribution simulation of a serial link transceiver including channel and circuit imperfections, such as finite pulse rise/fall time, duty cycle variation and both receiver and transmitter forwarded-clock jitter. A comparison between 20-Gb/s NRZ and duobinary transmitters using this simulator shows that while duobinary transmission relaxes the requirements on the receiver equalizer due to the lower Nyquist frequency of the transmitted data, significant eye-opening and BER degradation can arise from clock non-idealities. The proposed statistical analysis is verified against traditional time-domain, transient eye-diagram simulations at 20-Gb/s, transmitted through measured s-parameter channel characteristics.

A low-power, capacitively-divided, ring oscillator with digitally adjustable voltage swing

A capacitively-divided, injection-locked, ring oscillator is proposed that decreases dynamic power consumption by reducing voltage swing. A feedforward capacitor is placed in series with the load capacitance, effectively AC coupling each inverter stage to the next stage. Simulations are performed using digital programmability of the capacitor weights of both the feedforward and load capacitors, showing a reduction in the power consumption by as much as 36% with a 72% reduction in voltage swing. At the limits of reduced voltage swing, the power consumption is limited by static leakage current. Built in a 1.2V, 90nm CMOS process, the proposed capacitively-coupled, ring oscillator with digital trimming is injection-locked to an off-chip reference clock, with the measurement results verifying the correctness of the simulated performance.

Low-power 8Gb/s near-threshold serial link receivers using super-harmonic injection locking in 65nm CMOS

A testchip of 8Gb/s forwarded clock serial link receivers is presented. The receiver exploits a novel low-power super-harmonic injection-locked ring oscillator for symmetric multi-phase local clock generation and dekewing. Further power reduction is achieved by designing most the receiver circuits in the near-threshold region of 0.6V supply, with the exception of only the global clock buffer, test buffers and synthesized digital circuits at nominal 1V supply. At architectural level, 1∶10 direct demultiplexing rate is chosen as a demonstration of achieving low supply operation by high-parallelism design. Fabricated in 65nm CMOS technology, two receiver prototypes are integrated in this testchip, one without and the other with front S/Hs. Including the amortized power of global clock distribution, they consume 1.3mW and 2mW respectively at 8Gb/s input data rate, which achieve the power efficiency of 0.163mW/Gb/s and 0.25mW/Gb/s. Measurement results show both receivers get BER &#60; 10−12 across a 20-cm FR4 PCB channel.

Comparison of on-die global clock distribution methods for parallel serial links

This paper presents a comparative study of clock distribution methods for serial links, including inverter chain, CML chain, transmission line, inductive load and capacitively driven wires in regards to delay, jitter and power consumption. Analysis, simulation and design insights are given for each method for 2.5GHz clock propagation by on-die 5mm wire in a 90nm CMOS process. Simulations show the transmission line achieves least jitter and delay, while capacitively driven wire illustrates the best power-jitter and power-delay product.