Changku Hwang

A low-voltage low-power wide-range CMOS variable gain amplifier

In this paper, a compact low-power (LP) low-voltage (LV) metal-oxide-semiconductor-only (MOS-only) variable gain amplifier (VCA) is introduced. This amplifier based on complementary MOS (CMOS) transistors operating in strong inversion is composed of a pseudo-exponential current-to-voltage converter, analog multiplier, and output stage. The gain of the amplifier is controlled exponentially by a novel wide-range pseudo-exponential current-to-voltage converter implemented with two back-to-back connected current mirrors exhibiting superb exponential characteristic. Also, a new LV/LP composite transistor is introduced to increase the input dynamic range of the multiplier. The amplifier is fabricated using a 2-/spl mu/m MOSIS n-well process, and its simulation and measurement results are shown in detail.

Universal constant-g/sub m/ input-stage architectures for low-voltage op amps

In this paper, a novel design technique for low-voltage, constant transconductance (g/sub m/) op amp input stages is presented. The new technique which uses current-mode circuits is based on processing signal currents, rather than handling DC tail currents, to achieve a constant-g/sub m/. Two cases are developed. One is based on processing signal currents (the AC case) while the other is based on processing total instantaneous currents (the TIC case). The adopted design strategy in both cases is universal in that it is independent of the input stage transistor types (FET or bipolar) and their operating regions. It also considerably simplifies the design procedure of low-voltage op amps. To demonstrate the new concepts, universal op amp input stage architectures have been developed and their performances have been verified in both MOS and bipolar design examples. The MOS designs have been verified in both weak and strong inversion. The proposed universal implementations achieve almost constant-g/sub m/, independent of the common mode input voltage range from rail-to-rail.

A very low frequency, micropower, low voltage CMOS oscillator for noncardiac pacemakers

One of the most power consuming components of a modern noncardiac pacemaker is the oscillator circuitry. This brief details the design of a micropower, low voltage, low frequency oscillator consisting of CMOS devices operating in subthreshold. Since the frequency of a typical oscillator is proportional to Current/Capacitance, the operation of the transistors in the subthreshold region allows the size of the capacitance to be reduced significantly in addition to decreasing the quiescent power consumption. The proposed prototype oscillator was fabricated in a 2 /spl mu/m n-well CMOS process and occupies 0.281 mm/sup 2/ including a 100 pf capacitor which takes 77.8% (0.219 mm/sup 2/) of the total area. Experimental results show a frequency of oscillation as low as 0.3 Hz and a power consumption of around 0.24 /spl mu/W at 0.3 Hz to 0.3 /spl mu/W at 100 Hz with a 2 V supply voltage.

Low-Voltage CMOS Rail-to-Rail V-I Converters

This paper presents two CMOS low-voltage rail-to-rail voltage-to-current converters (V-I converter) which could be used as basic building blocks to construct low-voltage current-mode analog VLSI circuits. In each of the circuits, an N-type V-I converter cell is connected in parallel with its P-type counterpart to achieve common-mode rail-to-rail operation. A linear differential relationship of the N-type V-I converter, or its P-type complement, is obtained using a new class-AB linearization technique. In the first rail-to-rail V-I converter circuit, a constant transconductance is achieved through the use of two maximum-current selecting circuits and an output subtraction stage. In the second circuit, a constant transconductance value is obtained by manipulating the DC bias currents of N- and P-type V-I converter cells. Both of the circuits can operate from rail to rail with a power supply of 3V, or less depending on the VLSI technology and the DC bias current level.

LV opamp with programmable rail-to-rail constant-g/sub m/

In this paper a new differential pair architecture with programmable rail-to-rail constant-g/sub m/ is presented and incorporated into an opamp. Since the architecture adopts a signal processing method to obtain constant-g/sub m/, it can be implemented in any complementary VLSI technology and it functions regardless of transistor operating regions. The experimental results of the proposed opamp show that the total transconductance is constant at any common mode input voltage (CMR) and programmed over very wide range simply by varying the bias current of the opamp. It is also shown that constant unity gain frequency and open loop gain are obtained at any CMR and total harmonic distortion is effectively reduced due to the constant-g/sub m/.

On-Chip I/sub DDQ/ testability schemes for detecting multiple faults in CMOS ICs

In this paper we present two on-chip design-for-testability (DFT) schemes for CMOS ICs. One is for small circuits and the other for large circuits. Both schemes identify a faulty area on a chip with only a small area overhead for the additional circuitry and at most two extra pins. Moreover, if faults occur in different areas, multiple faults can also be detected with the proposed schemes. To demonstrate the ideas, DFT is incorporated in a 4-bit carry look ahead adder/subtractor (CLAAS) as well as a 16-bit arithmetic logic unit (ALU). Simulation results are given.

CMOS low-voltage rail-to-rail V-I converter

A low-voltage rail-to-rail voltage/current-controlled voltage-to-current converter, which is first order insensitive to the threshold voltage variation, is introduced. This circuit can be used as a basic building block to construct low-voltage current-mode analog computational circuits, which can perform functions such as square-rooting, squaring, multiplication, sum of squares, difference of squares and etc. First, a low-voltage N-type V-I converter cell is presented. A complementary P-type V-I converter is used in parallel with the N-type V-I converter to achieve common-mode rail-to-rail operation. Moreover, to achieve a constant transconductance of the V-I converter, P-type and N-type bias control circuits are utilized to provide bias currents. Finally, SPICE simulations results are given. The variation of the transconductance is shown to be less than 5%.

A simple universal LV/LP opamp architecture

In this paper a simple opamp input stage architecture with programmable rail-to-rail constant-g/sub m/ is presented. The constant-g/sub m/ is achieved by processing signal, rather than DC, currents. As a result, the architecture is universal in that it can be implemented in any complementary VLSI technology and it functions regardless of transistors operating region. A MOS implementation is discussed and is shown to operate in both weak and strong inversion, resulting in a programmable g/sub m/, or unity gain frequency, over a very wide range.

LV CMOS high speed analog multiplier

In this paper we propose a new low voltage high-speed CMOS composite transistor. This new transistor with a 3 dB bandwidth of 444 MHz; lowers supply voltage down to |V/sub t/|+2V/sub ds, sat/ and extends input voltage operating range to 1.8 V with a 3 V supply. These features together with the two high input impedance terminals provided by the composite transistor leads to the design of a high-speed four quadrant analog multiplier. All simulations have been carried out using MOSIS 2 /spl mu/m N-well process with a 8 V supply. The results show that the multiplier can operate with a maximum differential input of 1 V/sub pp/ and /spl omega//sub -3 dB/ of 305 MHz.

A programmable low-voltage micropower CMOS input stage architecture

A very simple CMOS rail-to-rail, constant-g/sub m/ opamp input stage architecture is presented. The constant-g/sub m/ is achieved by processing signal currents rather than DC bias currents. As a result, the architecture is universal in that it operates in both weak and strong inversion regions with small variations in g/sub m/.