Younsuk Kim

Power-Combining Transformer Techniques for Fully-Integrated CMOS Power Amplifiers

Fully integrated CMOS power amplifiers (PAs) with parallel power-combining transformer are presented. For the high power CMOS PA design, two types of transformers, series-combining and parallel-combining, are fully analyzed and compared in detail to show the parasitic resistance and the turn ratio as the limiting factor of power combining. Based on the analysis, two kinds of parallel-combining transformers, a two-primary with a 1:2 turn ratio and a three-primary with a 1:2 turn ratio, are incorporated into the design of fully-integrated CMOS PAs in a standard 0.18-mum CMOS process. The PA with a two-primary transformer delivers 31.2 dBm of output power with 41% of power-added efficiency (PAE), and the PA with a three-primary transformer achieves 32 dBm of output power with 30% of PAE at 1.8 GHz with a 3.3-V power supply.

A 1.9-GHz CMOS Power Amplifier Using Three-Port Asymmetric Transmission Line Transformer for a Polar Transmitter

A 1.9-GHz CMOS differential power amplifier for a polar transmitter is implemented with a 0.18-mum RF CMOS process. All of the matching components, including the input and output transformers, are fully integrated. The concepts of injection locking and variable load are applied to increase the efficiency and dynamic range of the amplifier. An asymmetric three-port transmission line transformer is proposed to embody the variable load effectively. The power amplifier achieved a power-added efficiency of 40% at a maximum output power of 32 dBm. The dynamic range was 20 dB at supply voltages ranging from 0.5 to 3.3 V. The improvement of the low power efficiency was 290% at an output power of 16 dBm

Stowage planning in maritime container transportation

We consider a stowage-planning problem of arranging containers on a container ship in the maritime transportation system. Since containers are accessible only from the top of the stack, temporary unloading and reloading of containers, called shifting, is unavoidable if a container required to be unloaded at the current port is stacked under containers to be unloaded at later ports on the route of the ship. The objective of the stowage planning problem is to minimize the time required for shifting and crane movements on a tour of a container ship while maintaining the stability of the ship. For the problem, we develop a heuristic solution method in which the problem is divided into two subproblems, one for assigning container groups into the holds and one for determining a loading pattern of containers assigned to each hold. The former subproblem is solved by a greedy heuristic based on the transportation simplex method, while the latter is solved by a tree search method. These two subproblems are solved iteratively using information obtained from solutions of each other. To see the performance of the suggested algorithm, computational tests are performed on problem instances generated based on information obtained from an ocean container liner. Results show that the suggested algorithm works better than existing algorithms.

A Lagrangian relaxation approach to multi-period inventory/distribution planning

We consider a multi-period inventory/distribution planning problem (MPIDP) in a one-warehouse multiretailer distribution system where a fleet of heterogeneous vehicles delivers products from a warehouse to several retailers. The objective of the MPIDP is to minimise transportation costs for product delivery and inventory holding costs at retailers over the planning horizon. In this research, the problem is formulated as a mixed integer linear programme and solved by a Lagrangian relaxation approach. A subgradient optimisation method is employed to obtain lower bounds. We develop a Lagrangian heuristic algorithm to find a good feasible solution of the MPIDP. Computational experiments on randomly generated test problems showed that the suggested algorithm gave relatively good solutions in a reasonable amount of computation time.

A Monolithic Voltage-Boosting Parallel-Primary Transformer Structures for Fully Integrated CMOS Power Amplifier Design

In this paper, a novel monolithic voltage-boosting parallel-primary transformer is presented for the fully integrated CMOS power amplifier design. Multiple primary loops are interweaved in parallel to combine the AC currents from multiple power devices while the higher turn ratio of a secondary loop boosts AC voltages of the combined primary loops at the load of the secondary loop. The proposed interweaved structure is much more compact and separable from power devices, avoiding potential instability. To verify the feasibility of this power combining method, the fully integrated CMOS switching power amplifier was implemented in a standard 0.18-mum technology. The power amplifier successfully demonstrated a measured output power of 1.3 W and a measured power added efficiency (PAE) of 41% to a 50-Omega load with a 3.3-V power supply at 1.8 GHz operation.

A Load-Shared CMOS Power Amplifier With Efficiency Boosting at Low Power Mode for Polar Transmitters

A load-shared CMOS power amplifier (PA) for 1.8-GHz polar transmitter applications has been implemented in standard 0.18-mum CMOS technology and fully characterized to demonstrate its efficiency boosting technique in low power mode. With the aid of cascode amplifiers, the load-shared configuration achieves efficiency improvement at low supply voltage in a polar transmitter. A differential class-E amplifier with a parallel resonant circuit is analyzed and incorporated in the load-shared PA. The load-shared configuration is composed of driver amplifiers (DAs) and PAs whose output loads are shared. The DA has a constant gate voltage biasing of a cascode amplifier for efficiency boosting, whereas the PA has a self-biased cascode configuration to be turned on and off by a supply voltage. The measurement results of the load-shared configuration show a drain efficiency increase from 6% to 30% at 16-dBm output power compared with a conventional self-biased cascode amplifier. The load-shared PA is reported with 35.6% of power-added efficiency and 32.2 dBm of output power at 1.88 GHz.

A 1.9-GHz Triple-Mode Class-E Power Amplifier for a Polar Transmitter

A 1.9-GHz CMOS power amplifier for polar transmitters was implemented with a 0.25-mum radio frequency CMOS process. All the matching components, including the input and output transformers, were fully integrated. The concepts of mode locking and adaptive load were applied in order to increase the efficiency and dynamic range of the amplifier. The amplifier achieved a drain efficiency of 33% at a maximum output power of 28dBm. The measured dynamic range was 34dB for a supply voltage that ranged from 0.7 to 3.3V. The measured improvement of the low power efficiency was 140% at an output power of 16dBm

A 1.8-GHz 2-Watt Fully Integrated CMOS Push-Pull Parallel-Combined Power Amplifier Design

This paper newly presents a push-pull parallel-combined CMOS power amplifier (PA) and its analysis of operation. The proposed class-E CMOS PA incorporates the push-pull parallel-combined power devices with the 1:1:2 (two single-turn primary windings and a two-turn secondary winding) step-up on-chip transformer. The PA is fully integrated in a standard 0.18-mum CMOS technology without any external balun or matching networks. The operation of the PA with a multi-turn on-chip transformer is substantially analyzed in order to optimize the device size and its structure. Experimental data demonstrates the output power of 2-watt and the power-added efficiency (PAE) of more than 30% with a 3.3-V of power supply at 1.8 GHz. This is the new demonstration of the compact fully integrated CMOS PA with 2-watt of output power with very stable operation at 1.8 GHz range.

Scheduling healthcare services in a home healthcare system

We consider a scheduling problem in a home healthcare system in which nurses visit patients regularly for relatively minor healthcare services. Intervals between the visits may differ for different patients. On each day in the planning horizon, a nurse must visit the patients assigned to her/him on that day, and then return to the hospital. For the problem of determining the visiting schedule with the objective of minimizing total travel time of the nurse over the planning horizon, we develop a two-phase heuristic algorithm. To evaluate performance of the proposed algorithm, a series of computational tests is performed on a number of randomly generated problem instances and a real instance. Results of the tests show that the heuristic algorithm gives near optimal solutions for problems of practical sizes in a reasonable time.

A fully-integrated 900-MHz CMOS power amplifier for mobile RFID reader applications

A 900-MHz linear power amplifier has been fabricated for ultra-high-frequency (UHF) radio frequency identification (RFID) reader applications using a 0.25-mum CMOS technology. An on-chip transmission-line transformer is used for output matching network. Input and inter-stage matching components, and RF chokes are fully integrated in the designed amplifier so that no external components are required. The power amplifier provides linear output power of 27 dBm at 920 MHz with a 2.5-V supply. Power-added-efficiency (PAE) at 1-dB-gain-compression point (P1dB) is 28 %. Gain flatness over the full UHF RFID band, which covers from 860 MHz to 960 MHz, is 1 dB