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Dive into the research topics where Changkyo Lee is active.

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Featured researches published by Changkyo Lee.


international solid-state circuits conference | 2017

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme

Changkyo Lee; Yoon-Joo Eom; Jin-Hee Park; J.G. Lee; Hye-Ran Kim; Kihan Kim; Young Choi; Ho-Jun Chang; Jong-Hyuk Kim; Jong-Min Bang; Seung-jun Shin; Hanna Park; Su-Jin Park; Young-Ryeol Choi; Hoon Lee; Kyong-Ho Jeon; Jae-Young Lee; Hyo-Joo Ahn; Kyoung-Ho Kim; Jung-Sik Kim; Soo-bong Chang; Hyong-Ryol Hwang; Du-Yeul Kim; Yoon-Hwan Yoon; Seok-Hun Hyun; Joon-Young Park; Yoon-Gyu Song; Youn-sik Park; Hyuckjoon Kwon; Seung-Jun Bae

With growing demand for low-power mobile applications, such as wearable devices, smart phones and tablet PCs, low-power mobile DRAM has been identified as a mandatory requirement for low-power system designs. The recently developed LPDDR4 [1] is still a power efficient solution because of its architectural approaches and low-voltage-swing terminated logic (LVSTL). However, demand for enhanced power-efficiency beyond LPDDR4 is still increasing for mobile applications. In this work, a 5.0Gbp/s/pin 8Gb LPDDR4X memory with power-isolated low-voltage-swing terminated logic (PI-LVSTL) and a split-die architecture is proposed to enhance power-efficiency and mass production yield.


symposium on vlsi circuits | 2015

A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface

Changkyo Lee; Min-Su Ahn; Daesik Moon; Ki-ho Kim; Yoon-Joo Eom; Won-Young Lee; Jongmin Kim; Sanghyuk Yoon; Baekkyu Choi; Seokhong Kwon; Joon-Young Park; Seung-Jun Bae; Yong-Cheol Bae; Jung-Hwan Choi; Seong-Jin Jang; Gyo-Young Jin

A 6.4Gb/s TX-interleaving (TI) technique at sub-1V supply voltage is implemented with 25nm DRAM process for the future mobile DRAM interface which requires 51.2 GBps (2X Bandwidth of LPDDR4). A newly proposed 2-channel TX interleaving technique with a bootstrapping switch can save power consumption drastically by eliminating repeaters, while operating at 6.4 Gb/s with 40 % enhancement of I/O power efficiency compared to that of the LPDDR4.


Proceedings of SPIE | 2014

Real-time 3D human pose recognition from reconstructed volume via voxel classifiers

ByungIn Yoo; Changkyu Choi; Jae-Joon Han; Changkyo Lee; Wonjun Kim; Sungjoo Suh; Du-sik Park; Junmo Kim

This paper presents a human pose recognition method which simultaneously reconstructs a human volume based on ensemble of voxel classifiers from a single depth image in real-time. The human pose recognition is a difficult task since a single depth camera can capture only visible surfaces of a human body. In order to recognize invisible (self-occluded) surfaces of a human body, the proposed algorithm employs voxel classifiers trained with multi-layered synthetic voxels. Specifically, ray-casting onto a volumetric human model generates a synthetic voxel, where voxel consists of a 3D position and ID corresponding to the body part. The synthesized volumetric data which contain both visible and invisible body voxels are utilized to train the voxel classifiers. As a result, the voxel classifiers not only identify the visible voxels but also reconstruct the 3D positions and the IDs of the invisible voxels. The experimental results show improved performance on estimating the human poses due to the capability of inferring the invisible human body voxels. It is expected that the proposed algorithm can be applied to many fields such as telepresence, gaming, virtual fitting, wellness business, and real 3D contents control on real 3D displays.


Archive | 2015

Method and apparatus for recognizing object, and method and apparatus for training recognizer

ByungIn Yoo; Namjoon Kim; Changkyo Lee; Chang Kyu Choi; Jae-Joon Han


Archive | 2015

METHOD AND APPARATUS FOR EXTRACTING IMAGE FEATURE

Changkyo Lee; ByungIn Yoo; Namjoon Kim; Jae-Joon Han


Archive | 2016

METHOD AND APPARATUS FOR EXTRACTING FACIAL FEATURE, AND METHOD AND APPARATUS FOR FACIAL RECOGNITION

Namjoon Kim; ByungIn Yoo; Changkyo Lee; Jae-Joon Han


international solid-state circuits conference | 2018

A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

Ki Chul Chun; Yong-Gyu Chu; Jinseok Heo; Taesung Kim; Soo-Hwan Kim; Hui-Kap Yang; Mi-Jo Kim; Changkyo Lee; Kim Jy; Hyun-Chul Yoon; Chang-Ho Shin; Sang-Uhn Cha; Hyung-Jin Kim; Young-Sik Kim; K. Kim; Young-Ju Kim; Won-Jun Choi; Dae-Sik Yim; Inkyu Moon; J.G. Lee; Young Choi; Yongmin Kwon; S. Choi; Jung-Wook Kim; Yoon-Suk Park; Woongdae Kang; Jinil Chung; Seung-Hyun Kim; Ye-sin Ryu; Seong-Jin Cho


Archive | 2018

EYE DETECTION METHOD AND APPARATUS

Jae Joon Han; Changkyo Lee; Wonjun Hwang; Jung-Bae Kim


IEEE Journal of Solid-state Circuits | 2018

Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage–Frequency Scaling in LPDDR4 SDRAM

Changkyo Lee; J.G. Lee; Ki-ho Kim; Jinseok Heo; Jin-Hyeok Baek; Gil-Hoon Cha; Daesik Moon; Dong Hun Lee; Jong-Wook Park; Seunseob Lee; Si-Hyeong Cho; Young-Ryeol Choi; Kyung-Soo Ha; Eunsung Seo; Youn-sik Park; Seung-Jun Bae; In-Dal Song; Seok-Hun Hyun; Hyuckjoon Kwon; Young-Soo Sohn; Jung-Hwan Choi; Kwang-Il Park; Seong-Jin Jang


asian solid state circuits conference | 2017

Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM

Changkyo Lee; J.G. Lee; Ki-ho Kim; Jinseok Heo; Gil-Hoon Cha; Jin-Hyeok Baek; Daesik Moon; Yoon-Joo Eom; Taesung Kim; Hyunyoon Cho; Young Hoon Son; Seong-Hwan Kim; Jong-Wook Park; Sewon Eom; Si-Hyeong Cho; Young-Ryeol Choi; Seungseob Lee; Kyoung-Soo Ha; Young-Seok Kim; Bo-Tak Lim; Dae-Hee Jung; Eungsung Seo; Kyoung-Ho Kim; Yoon-Gyu Song; Youn-sik Park; Tae-Young Oh; Seung-Jun Bae; In-Dal Song; Seok-Hun Hyun; Joon-Young Park

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