J.G. Lee

Weak-microcavity organic light-emitting diodes with improved light out-coupling

We propose and demonstrate weak-microcavity organic light-emitting diode (OLED) displays with improved light-extraction and viewing-angle characteristics. A single pair of low- and high-index layers is inserted between indium tin oxide (ITO) and a glass substrate. The electroluminescent (EL) efficiencies of discrete red, green, and blue weak-microcavity OLEDs are enhanced by 56%, 107%, and 26%, respectively, with improved color purity. Moreover, full-color passive-matrix bottom-emitting OLED displays are fabricated by employing low-index layers of two thicknesses. As a display, the EL efficiency of white color was 27% higher than that of a conventional OLED display.

Color-tunable, phosphor-free InGaN nanowire light-emitting diode arrays monolithically integrated on silicon

We demonstrate controllable and tunable full color light generation through the monolithic integration of blue, green/yellow, and orange/red InGaN nanowire light-emitting diodes (LEDs). Such multi-color nanowire LED arrays are fabricated directly on Si substrate using a three-step selective area molecular beam epitaxy growth process. The lateral-arranged multi-color subpixels enable controlled light mixing at the chip-level and yield color-tunable light emission with CCT values in the range from 1900 K to 6800 K, while maintaining excellent color rendering capability. This work provides a viable approach for achieving micron and nanoscale tunable full-color LED arrays without the compromise between the device efficiency and light quality associated with conventional phosphor-based LEDs.

Bulk planar 20nm high-k/metal gate CMOS technology platform for low power and high performance applications

A 20 nm logic device technology for low power and high performance application is presented with the smallest contacted-poly pitch (CPP) of minimal 80 nm ever reported in bulk Si planar device. We have achieved nFET and pFET drive currents of 770 µA/µm and 756 µA/µm respectively at 0.9 V and 1 nA/µm Ioff with the novel high-k/metal (HKMG) gate stack and advanced strain engineering. Short channel effect is successfully suppressed thanks to the optimized shallow junction, resulting in excellent DIBL and subthreshold swing below 120 mV and 90 mV/dec, respectively. In addition, full functionality of SRAM device with 20 nm technology architecture is confirmed.

A 0.13 /spl mu/m DRAM technology for giga bit density stand-alone and embedded DRAMs

In this paper, a 0.13 /spl mu/m DRAM technology is developed with KrF lithography. In order to extend KrF lithography to 0.13 /spl mu/m generation, full CMP technology is developed in order to provide flat surface. Full self-aligned contact (SAC) technology can make memory cell processes easy because memory cell landing pads and storage node contact plug can be formed with self-aligned manner respect to word-line and bit-line. By these technologies, the extremely small memory cell is easily realized without any yield loss. Low-temperature PAOCS MIS capacitor with Al/sub 2/O/sub 3/ can greatly reduce the aspect ratio of metal contact, thereby yielding stable metal contact process. And it can help DRAM technology easily to merge with logic process. The 0.13 /spl mu/m integration technology is successfully demonstrated with 1 Gb DRAM.

Comprehensive extensibility of 20nm low power/high performance technology platform featuring scalable high-k/metal gate planar transistors with reduced design corner

Extensibility of the high-k/metal gate (HK/MG) planar devices beyond 20nm node with high performance, low power consumption, less layout dependence and suppressed local variability were comprehensively studied among gate first (GF) and gate-last (GL) schemes for the first time. We demonstrated the N-/PFET drive current (Idsat) of 1.45/1.3 mA/μm with the off-leakage current (Ioff) of 100 nA/μm for the Vdd of 0.9V by scaling down the gate width (Wg) of GL-HK/MG devices to 60nm. Key layout dependence of the PFET with embedded SiGe source/drain (eSiGe) was improved by eSiGe interface engineering and scaling down the Wg with keeping the multiple threshold voltage (Vt) and improving the body-bias effect (BE). Moreover, we demonstrated reduction in the capacitance by conventional method even for such a scaled planar device. Finally, we achieved the sufficiently low Vt mismatch, which is required to reduce the design corner, by eSiGe interface engineering and reduction of interface states in the gate stack (Dit).

Improvement of data retention time in DRAM using recessed channel array transistors with asymmetric channel doping for 80 nm feature size and beyond

A 512 Mb DRAM using a recessed channel array transistor with asymmetric channel doping scheme (RCAT-ASC) is fabricated for the first time with 80 nm feature size. We have found that RCAT-ASC shows much better device performance than the normal RCAT-SC (recessed channel array transistor with symmetric channel doping scheme) or PCAT-ASC (planar channel array transistor with asymmetric channel doping scheme). The RCAT-ASC has the lowest junction leakage currents at storage nodes among them. The increase of data retention time is found to be very remarkable, and thus we suggest that the RCAT-ASC should be an effective method for longer data retention time of DRAM for the future generations. Additionally, we also found that the charge sharing time (tCS) of RCAT-ASC has the lowest values among the three array transistor schemes.

Highly manufacturable 90 nm DRAM technology

A 90 nm DRAM technology has been successfully developed using 512 Mb DRAM for the first time. ArF lithography is used for printing critical layers with resolution enhancement techniques. A novel gap-filling technology using spin coating oxide is developed for STI and ILD processes. A diamond-shaped storage node is newly developed for large capacitor area with better mechanical stability. A CVD Al process can make the back-end metallization process simple and easy. A dual gate oxide scheme can provide independent optimization for memory cell transistor and periphery support device so that the off-state leakage current of the cell transistor can be maintained below 0.1 fA.

Simultaneously formed storage node contact and metal contact cell (SSMC) for 1 Gb DRAM and beyond

Simultaneously formed Storage node contact and Metal contact Cell (SSMC) was investigated and developed with 0.18 /spl mu/m advanced KrF lithography as a promising candidate for the cell structure of 1 Gb DRAM and beyond, such as 4 Gb and 16 Gb DRAMs. SSMC can provide fast and reliable memory cell operation by reducing parasitic resistance between memory cell storage node and access transistor. Also SSMC can reduce the processing steps compared to the conventional COB (Capacitor Over Bit line) cell by forming storage node contact holes and metal contact hole at the same time. Furthermore, it is found that SSMC has many other advantages in terms of process margin, and wide application, for example in EML (embedded memory logic). Thus, SSMC is a promising cell structure for 1 Gb DRAM and beyond.

1.5×10−9 Ωcm2 Contact resistivity on highly doped Si:P using Ge pre-amorphization and Ti silicidation

Record-low contact resistivity (ρ_c) for n-Si, down to 1.5×10^-9 Q-cm², is achieved on Si:P epitaxial layer. We confirm that Ti silicidation reduces the pc for n-Si, while an additional Ge pre-amorphization implantation (PAI) before Ti silicidation further extends the pc reduction. In situ doped Si:P with P concentration of 2×10²¹ cm^-3 is used as the substrate, and dynamic surface anneal (DSA) boosts P activation. In addition, TiO_x based metal-insulator-semiconductor (MIS) contact is also studied on Si:P but is found to suffer from low thermal stability.

Novel DRAM cell transistor with asymmetric source and drain junction profiles improving data retention characteristics

A novel DRAM cell transistor with an asymmetric source and drain structure is proposed, for the first time, to realize reliable high density DRAM below 0.12 /spl mu/m. The new cell structure could provide the optimized source and drain junction profiles independently. The junction profile at the storage node (SN) was designed to reduce electric field to minimize junction leakage current and thereby improving data retention time. On the other hand, the junction profile at the bit-line direct contact node (DC) was designed to suppress short channel effects of a cell transistor. It is considered to be highly scalable for device scaling and to solve fine printing and precise alignment requirements. The validity of the approach was directly confirmed by improvement in the refresh times of 512 Mb DRAM which was fabricated with 0.12 /spl mu/m DRAM technology.