Seok-Hun Hyun

1.2V 1.6Gb/s 56nm 6F 2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture

As the workload and speed of a computer system increase, both the data bandwidth and capacity of main memory inevitably need to grow. However, the number of slots per channel is limited to maintain high bandwidth, making the capacity requirement difficult to meet. Another problem is that computer systems impose a limit on the supply of power since their power dissipation increases rapidly, where main memories account for roughly 15% of total power consumption. To address these issues, we design a 4Gb DDR3 SDRAM that supports a 1.2V supply voltage and 1.6Gb/s data rate.

Si-based optical I/O for optical memory interface

Optical interconnects may provide solutions to the capacity-bandwidth trade-off of recent memory interface systems. For cost-effective optical memory interfaces, Samsung Electronics has been developing silicon photonics platforms on memory-compatible bulk-Si 300-mm wafers. The waveguide of 0.6 dB/mm propagation loss, vertical grating coupler of 2.7 dB coupling loss, modulator of 10 Gbps speed, and Ge/Si photodiode of 12.5 Gbps bandwidth have been achieved on the bulk-Si platform. 2x6.4 Gbps electrical driver circuits have been also fabricated using a CMOS process.

Ultrathin gate oxide with a reduced transition layer grown by plasma-assisted oxidation

Ultrathin SiO2 grown by plasma-assisted oxidation (plasma oxide) has been investigated by high-resolution x-ray photoemission spectroscopy and medium energy ion scattering spectroscopy. We found that the plasma oxide grown at the low temperature of 400°C has a thinner transition layer than conventional thermal oxide. This thinner transition layer in the plasma oxide not only decreased the gate leakage current effectively, but also enhanced the reliability of the gate oxide. We attribute these electrical properties of the plasma oxide to the reduction of the transition layer.

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme

With growing demand for low-power mobile applications, such as wearable devices, smart phones and tablet PCs, low-power mobile DRAM has been identified as a mandatory requirement for low-power system designs. The recently developed LPDDR4 [1] is still a power efficient solution because of its architectural approaches and low-voltage-swing terminated logic (LVSTL). However, demand for enhanced power-efficiency beyond LPDDR4 is still increasing for mobile applications. In this work, a 5.0Gbp/s/pin 8Gb LPDDR4X memory with power-isolated low-voltage-swing terminated logic (PI-LVSTL) and a split-die architecture is proposed to enhance power-efficiency and mass production yield.

A 10 Gbit/s Si CMOS transimpedance amplifier with an integrated MSM photodetector for optical interconnections

A wideband preamplifier is designed and fabricated using a 0.18 /spl mu/m CMOS technology. The amplifier is heterogeneously integrated with a thin film InGaAs inverted MSM photodetector, and a successful demonstration at a bit rate of 10 Gbps is reported.

Investigation of hot carrier effects in n-MOSFETs thick oxide with HfSiON and SiON gate dielectrics

This paper reports the reliability characteristics of poly gated n-MOSFETs with HfSiON and SiON gate dielectrics in both thin and thick oxide of dual gate oxide scheme. Hot carrier stress (HCS) at Isub, max condition on thick oxide is found to be the most critical part among the various reliability concerns. Regardless of gate dielectric and gate oxide thickness, the degradation behavior of the condition of Isub, max and Vg=Vd HCS is mainly SS increase and Vth shift, respectively. Therefore, for precise evaluation of the device reliability, it is necessary that HC immunity at Isub, max stress should be checked in thick oxide transistor below 50 nm design rule era.

The development of dual gate poly scheme with plasma nitrided gate oxide for mobile high performance DRAMs: plasma process monitoring and the correlation with electrical results

The in-line plasma process monitoring was successfully performed with non-contact direct measurement (NCDM) tool and its results were well matched with those from devices. Using this monitoring method, we developed a plasma nitrided gate oxide process for mobile DRAMs with low operating voltage. We confirm that plasma nitrided gate oxide can block the boron penetration in DRAMs, which has higher thermal budget than other devices, and that the NCDM tool can be used for checking the degree of plasma nitridation. We assure that the NCDM tool is a time-effective tool for plasma nitridation process development.

A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface

A time-based (TB) receiver (RX) with a 2-tap TB decision feedback equalizer (DFE) is proposed for mobile DRAM interface. The TB RX consists of a voltage-to-time converter (VTC), a TB DFE, and a time comparator. The VTC converts the RX input voltage to a time difference between two VTC outputs by using the difference in clock-to-Q delays between two latches with different input offset voltages. The TB DFE inserts an additional delay to one of the two VTC outputs and bypasses the other VTC output to increase the time opening. The time comparator makes a decision with the first arriving edge of the two outputs of the TB DFE. While the feedback loop delay must be less than 1 UI for proper operation in the conventional voltage-based DFE, the TB DFE allows the feedback loop delay up to 1.43 UI in this paper. A transmitter (TX) transmits a single-ended signal of 200-mV swing by using an n-over-n voltage-mode driver. The transceiver in a 65-nm CMOS process achieves a 12.5 Gb/s with a 0.8-V supply through a 15-inch FR-4 channel of 14-dB loss. The TX and RX chip consume 4.3 and 3.4 mA, respectively. The energy efficiency is 0.49 pJ/b.

23.7 A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS

Single-ended transceivers are mostly used for DRAM interfaces to reduce pin count. A low-supply transceiver is preferred, especially for mobile DRAM interfaces, for low-power consumption while maintaining a high-speed interface for transmission of image data [1]. To reduce transmitter power in single-ended transceivers, both the supply voltage and the signal swing are reduced: 0.8V and 200mV, or below [2]. However, with a small signal swing the low-supply voltage limits the maximum data rate that can be handled by the receiver (RX); the maximum data rate reported is below 10Gb/s with a supply voltage of 0.8V in 65nm CMOS [2-4]. In a conventional RX at a low-supply voltage, the maximum data rate is limited by the small gm/C of the RX front-end circuit. To eliminate this gm/C constraint, this work proposes a time-based RX for 12Gb/s operation at 0.8V.