Changze Liu

Electrical properties of Cu doped p-ZnTe nanowires

Single crystalline zincblende p-ZnTe nanowires (NWs) were synthesized via the vapour phase transport method. Based on either as-grown or Cu doped ZnTe NWs, single NW field effect transistors were fabricated and they were used to study the electrical properties of ZnTe NWs. Electrical transport measurements show that the as-grown ZnTe NWs are of p-type and very high resistivity. After 30 min immersion in Cu(NO3)2 solution, their conductivity can be increased by about three orders of magnitude. The hole concentrations of the p-type ZnTe nanowires could be controlled in a range from 7.0 × 1017 to 3.5 × 1018 cm−3 by changing the immersion duration. The doped p-type ZnTe NWs may have potential applications in nanoscale electronic and optoelectronic devices.

A unified approach for trap-aware device/circuit co-design in nanoscale CMOS technology

In this paper, the major physical effects caused by gate oxide traps in MOSFETs have been integrated for the first time by a proposed unified approach in realistic manners based on industry-standard EDA tools, aiming at practical trap-aware device/circuit co-design. The recently-found AC or transient effects of traps and the interplays with manufacturing process variations are included, with demonstrations on two representatives (RO and SRAM) under realistic digital circuit operations. The proposed approach and the results are helpful for robust and resilient device/circuit co-design in future nano-CMOS technology.

New insights into AC RTN in scaled high-к / metal-gate MOSFETs under digital circuit operations

Since devices actually operate under AC signals in digital circuits, it is more informative to study random telegraph noise (RTN) at dynamic AC biases than at constant DC voltages. We found that the AC RTN statistics largely deviates from traditional DC RTN, in terms of different distribution functions and the strong dependence on AC signal frequency, which directly impacts on the accurate prediction of circuit stability and variability. The AC RTN characteristics in high-κ/metal-gate FETs are different from that in SiON FETs, and both of which cannot be described by classical RTN theory. A physical model based on quantum mechanics is proposed, which successfully explains the new observations of AC RTN. It is also demonstrated that, if using DC RTN statistics instead of AC RTN, a large error of 30% overestimation on the read failure probability in ultra-scaled SRAM cells will occur. These new understandings are critical for the robust circuit design against RTN in practical digital circuits.

Towards the systematic study of aging induced dynamic variability in nano-MOSFETs: Adding the missing cycle-to-cycle variation effects into device-to-device variation

In this paper, the NBTI induced dynamic Vth variability in nano-scaled MOSFETs is comprehensively studied. In addition to the device-to-device variation (DDV) of NBTI degradation, the non-negligible cycle-to-cycle variation (CCV) due to the random occupation of trap states in each operation cycle is observed for the first time. By using the statistical trap-response (STR) technique, a new characterization scheme of the NBTI induced total ΔVth variation is proposed, combining both DDV (random spatial distribution of trap positions) and CCV together. This systematic study clarifies the superposition of the missing part of trap occupancy probability in the NBTI reliability induced dynamic variation. The single-trap occupancy behaviors as well as the comparison between DC/AC NBTI effects are also studied for microscopic understanding and accurate prediction of the dynamic Vth variation due to NBTI degradation in ultra-scaled devices.

New observations on AC NBTI induced dynamic variability in scaled high-κ/Metal-gate MOSFETs: Characterization, origin of frequency dependence, and impacts on circuits

In this paper, the frequency dependence of the dynamic variation induced by AC NBTI aging in scaled high-κ/metal-gate devices are experimentally studied for the first time. Challenges in comprehensively characterizing AC NBTI induced variation are addressed by the modified method. The additional variation source in AC NBTI, originating from the variations among each AC clock cycle, is found to be non-negligible and thus should be included in predicting circuit stability. With increasing AC frequency, the mean value (μ) of the Vth shift (ΔVth) is reduced as expected; however, the variation (σ) of ΔVth is almost unchanged, which surprisingly disagrees with the conventional model predicting the reduced variation. The origin of this new observation is found due to the competitive impacts of the activated trap number and the trap occupancy probability during device aging. Taken clock-CCV and frequency dependence into account, the impacts of AC NBTI on the SRAM cell stability can be evaluated in terms of both degradation and variation. The results are helpful for the future variability-aware circuit design.

Characterization and analysis of gate-all-around Si nanowire transistors for extreme scaling

The gate-all-around (GAA) silicon nanowire transistor (SNWT) is considered as one of the best candidates for ultimately scaled CMOS devices at the end of the technology roadmap. This paper reviews our recent work on the characterization and analysis of this unique one-dimensional nanowire-channel device with three-dimensional surrounding-gate from experiments and simulation, including carrier transport behavior, parasitic effects, noise characteristics, self-heating effect, variability and reliability, which can provide useful information for the GAA device hierarchical modeling and device/circuit co-design.

Experimental study on quasi-ballistic transport in silicon nanowire transistors and the impact of self-heating effects

The ballistic efficiency and self-heating effects in gate-all-around silicon nanowire transistors (SNWTs) are experimentally investigated in this paper. A modified experimental extraction method for SNWTs is proposed, which takes into account the impact of source contact resistance. The highest ballistic efficiency is observed in sub-40 nm SNWTs at room temperature, demonstrating their intrinsic potential for near-ballistic transport. However, it is experimentally found that, even if the SNWT is fabricated on bulk-Si substrate, the self-heating effect is comparable or even a little bit worse than SOI devices due to the 1-D nature of nanowire and increased phonon-boundary scattering in GAA structure. Considering heat transport and heating corrections at the drain side, the Lundstrom model is modified, and the impacts of self-heating on quasi-ballistic SNWTs are discussed as well.

New observations on complex RTN in scaled high-κ/metal-gate MOSFETs — The role of defect coupling under DC/AC condition

The coupling effect between multi-traps in complex RTN is experimentally studied in scaled high-κ/metal-gate MOSFETs for the first time. By using extended STR method, the narrow “test window” of complex RTN is successfully expanded to full VG swing. Evident defect coupling can be observed in both RTN amplitude and time constants. Interesting nonmonotonic bias-dependence of defect coupling is found, which is due to two competitive mechanisms of Coulomb repulsion and channel percolation conduction. The decreased defect coupling is observed with increasing AC frequency. Based on the new observations on complex RTN, its impacts on the circuit stability are also evaluated, which show an underestimation of the transient performance if not considering defect coupling. The results are helpful for future robust circuit design against RTN.

New understanding of the statistics of random telegraph noise in Si nanowire transistors - the role of quantum confinement and non-stationary effects

In this paper, the random telegraph noise (RTN) statistics in silicon nanowire transistors (SNWTs) are comprehensively studied. The capture/emission time constants and probabilities are found to be strongly impacted by the quantum confinement in SNWTs, which cannot be fully explained by classical RTN theory. A full quantum RTN model for SNWTs is proposed for fundamental understanding of the experiments. The characteristics of non-stationary RTN in SNWTs under high-field biases are studied for the first time, based on the developed statistical trap-response (STR) characterization method. The trap capture probability is found to be much different from that of the quasi-stationary RTN, leading to large errors in circuit aging prediction if using traditional RTN distributions. These new understandings are critical for robust SNWT circuit design against RTN.

Oxide-based RRAM: Requirements and challenges of modeling and simulation

New physical insights on the underlying physics from switching behaviors to operating mechanisms of oxide-based RRAM are presented by taking the microstructure nature of switching materials and correlated physical effects with switching process into account. Based on the new physical insights, a platform for HfOx- and TaOx-based RRAM including simulation tools and compact models is developed, which is able to reproduce the essential electrical and microscopic characteristics of RRAM and bridge the link between device and circuit systems, meeting the requirements of device-circuit-system co-design and optimization.