Jiewen Fan

Insight Into Gate-Induced Drain Leakage in Silicon Nanowire Transistors

In this paper, detailed physical mechanisms of gate-induced drain leakage (GIDL) in gate-all-around silicon nanowire transistors (SNWTs) are investigated and verified by experiments and TCAD studies. The results show that the SNWTs will suffer from a more severe GIDL issue in small diameter (Dnw) devices under low IVgsI. It is believed that this unexpected GIDL problem in SNWTs origins from the longitudinal band-to-band tunneling (L-BTBT) at the body/drain junction enhanced by the strong gate coupling to the depletion region, which usually can be neglected in planar devices. On the other hand, the traditional transverse BTBT (T-BTBT) only dominates at high IVgsI with relatively large Dnw. Systematic study of GIDL dependence on process parameters, including Dnw cross-sectional shape, doping, and overlap length (Lov), shows that both T-BTBT and L-BTBT can be alleviated by reducing the doping and rounding the corner, but L-BTBT is worsened by reducing Dnw and Lov despite of the alleviated T-BTBT. As the extension process engineering strongly impacts the short-channel effect and driving current of SNWTs, a GIDL optimization strategy considering the leakage power and device performance is given for low-power SNWT design.

Investigations on Line-Edge Roughness (LER) and Line-Width Roughness (LWR) in Nanoscale CMOS Technology: Part II–Experimental Results and Impacts on Device Variability

In the part I of this paper, the correlation between line-edge roughness (LER) and line-width roughness (LWR) is investigated by theoretical modeling and simulation. In this paper, process-dependence of the correlation between LER and LWR is studied. The experimental results indicate that both Si Fin and nanowire have strongly correlated LER/LWR, and the cross-correlation of two edges depends on the fabrication process. Based on the improved simulation method proposed in the Part I of this paper, the impacts of correlated LER/LWR in the channel of double-gate devices are investigated. The results show that Vth distribution strongly relies on cross-correlation, and can exhibit non-Gaussian distribution and/or multipeak distribution, which enlarges the Vth variation.

Characterization and analysis of gate-all-around Si nanowire transistors for extreme scaling

The gate-all-around (GAA) silicon nanowire transistor (SNWT) is considered as one of the best candidates for ultimately scaled CMOS devices at the end of the technology roadmap. This paper reviews our recent work on the characterization and analysis of this unique one-dimensional nanowire-channel device with three-dimensional surrounding-gate from experiments and simulation, including carrier transport behavior, parasitic effects, noise characteristics, self-heating effect, variability and reliability, which can provide useful information for the GAA device hierarchical modeling and device/circuit co-design.

New understanding of the statistics of random telegraph noise in Si nanowire transistors - the role of quantum confinement and non-stationary effects

In this paper, the random telegraph noise (RTN) statistics in silicon nanowire transistors (SNWTs) are comprehensively studied. The capture/emission time constants and probabilities are found to be strongly impacted by the quantum confinement in SNWTs, which cannot be fully explained by classical RTN theory. A full quantum RTN model for SNWTs is proposed for fundamental understanding of the experiments. The characteristics of non-stationary RTN in SNWTs under high-field biases are studied for the first time, based on the developed statistical trap-response (STR) characterization method. The trap capture probability is found to be much different from that of the quasi-stationary RTN, leading to large errors in circuit aging prediction if using traditional RTN distributions. These new understandings are critical for robust SNWT circuit design against RTN.

Two-Dimensional Self-Limiting Wet Oxidation of Silicon Nanowires: Experiments and Modeling

In this paper, a CMOS compatible silicon nanowire (Si NW) fabrication method on bulk silicon substrate is carried out using the self-limiting oxidation (SLO) to accurately control its size and cross-sectional shape. A predictive model for the 2-D SLO of Si NWs is presented. In this model, both the reduced reaction rate and diffusivity result in the oxidation rate degradation. The orientation dependence and the deformation of silicon core and oxide shell are further discussed here. The modeling results show good agreement with the experimental data within a wide range of oxidation temperatures, oxidation time, and various initial silicon core sizes. This model provides useful process design guidelines for Si nanostructures, especially in controlling the final diameter and cross-sectional shape of Si NWs from the top-down approach.

Total ionizing dose (TID) effect and single event effect (SEE) in quasi-SOI nMOSFETs

This paper studies the total ionizing dose (TID) and single event effect (SEE) in quasi-SOI nMOSFETs for the first time. After exposure to gamma rays, the off-state leakage current (Ioff) of a quasi-SOI device increases with the accumulating TID, and the on-state bias configuration is shown to be the worst-case bias configuration during irradiation. Although an additional TID-sensitive region is introduced by the unique structure of the quasi-SOI device, the influence of positive charge trapped in L-type oxide layers on the degradation of device performance is neglectable. Since the TID-induced leakage path in the quasi-SOI device is greatly reduced due to the isolation of L-type oxide layers, the TID-induced Ioff degradation in the quasi-SOI device is greatly suppressed. In addition, 3D simulation is performed to investigate the SEE of the quasi-SOI device. The full-width at half-maximum (FWHM) of worst-case drain current transient and collected charges of the quasi-SOI device after single-ion-striking is smaller than in a bulk Si device, indicating that the quasi-SOI device inherits the advantage of an SOI device in single event transient immunity. Therefore, the quasi-SOI device, which has improved electrical properties and radiation-hardened characteristics for both TID and SEE, can be considered as one of the promising candidates for space applications.

New observation on gate-induced drain leakage in Silicon nanowire transistors with Epi-Free CMOS compatible technology on SOI substrate

As a promising transistors beyond 22nm technology node, Silicon nanowire (Si NW) transistor has attracted a lot of attentions recently [1]-[4]. Due to its unique gate-all-around (GAA) structure, Si NW transistor provides enhanced gate controllability and reduced sub-threshold leakage. However, gate-induced drain leakage (GIDL) as another primary leakage mechanism is still challenging [5][6]. In addition, due to the lateral parasitic bipolar junction transistor (PBJT), GIDL can be further enhanced in floating body transistors including Si NW transistor [7]. Unfortunately, few work on the origin sources and mechanism of GIDL in Si NW transistors have been reported up to now. In this paper, we have successfully fabricated Si NW transistors of high driving current with diameter down to 10nm on SOI substrate. More serious GIDL at low |Vgs| in Si NW transistor is observed compared with planar devices, which results from the strong gate-controlled longitudinal band-to-band tunneling (L-BTBT) of Si NW transistor, rather than traditional vertical BTBT in planar device. The dependence of GIDL on geometry parameters is also evaluated for further optimization.

Voltage-Controlled Magnetoresistance in Silicon Nanowire Transistors

Magneto-electronic logic is an innovative approach to performing high-efficiency computations. Additionally, the ultra-large scale integration requirement for computation strongly suggests exploiting magnetoresistance effects in non-magnetic semiconductor materials. Here, we demonstrate the magnetoresistance effect in a silicon nanowire field effect transistor (SNWT) fabricated by complementary metal-oxide-semiconductor (CMOS)-compatible technology. Our experimental results show that the sign and the magnitude of the magnetoresistance in SNWTs can be effectively controlled by the drain-source voltage and the gate-source voltage, respectively, playing the role of a multi-terminal tunable magnetoresistance device. Various current models are established and in good agreement with the experimental results that describe the impact of electrical voltage and magnetic field on magnetoresistance, which provides design feasibility for the high-density magneto-electronic circuit. Such findings will further pave the way for nanoscale silicon-based magneto-electronics logic devices and show a possible path beyond the developmental limits of CMOS logic.

Investigation on Electrostatic Discharge Robustness of Gate-All-Around Silicon Nanowire Transistors Combined With Thermal Analysis

In this letter, we investigate the robustness of silicon-on-insulator-based gate-all-around silicon nanowire transistors (GAA SNWTs) subject to electrostatic discharge (ESD) stress by thermal analysis and transmission line pulse measurements.. The thermal conductance modeling shows that heat dissipation, from channel to substrate through gate oxide, gate electrode, and buried oxide, dominates the thermal failure mechanism and thus the intrinsic ESD performance in GAA SNWTs. Accordingly, a new GAA SNWT is proposed and fabricated. A record failure current density of 18.8 mA/

Multi-V T design of vertical channel nanowire FET for sub-10nm technology node

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