Chao-Cheng Lee

A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement

A low quiescent current asynchronous digital- LDO (D-LDO) regulator integrated with a phase-locked loop (PLL)-modulated switching regulator (SWR) that achieves the near-optimum power management supply for core processor in system-on-chip (SoC). The parallel connection of the asynchronous D-LDO regulator and the ripple-based control SWR can accomplish fast-DVS (F-DVS) operation as well as high power conversion efficiency. The asynchronous D-LDO regulator controlled by bidirectional asynchronous wave pipeline realizes the F-DVS operation, which guarantees high million instructions per second (MIPS) performance of the core processor under distinct tasks. The use of a ripple-based control SWR operating with a leading phase amplifier ensures fast response and stable operation without the need for large equivalent-series-resistance, thus reducing the output voltage ripple for the enhancement of supply quality. The fabricated chip occupies 1.04 mm2 in 40 nm CMOS technology. Experimental results show that a 94% peak efficiency with a voltage tracking speed of 7.5 V/μs as well as the improved MIPS performance by 5.6 times was achieved.

A 7b 1.1GS/s Reconfigurable Time-Interleaved ADC in 90nm CMOS

A time-interleaved pipeline ADC is designed with the reconfigurable resolution and sampling rate, Fs, to accommodate different operation scenarios. The main offset and gain mismatches between four sub-ADCs are modulated to the frequency of F/2 by the reference-and opamp-sharing techniques. Fabricated in 90 nm CMOS, the 7 bit ADC has an ENOB of 6.5 at 1.1 GHz sampling rate. The I/Q ADCs totally consume power of 92 mW from a 1.3 V supply.

A Near-Optimum Dynamic Voltage Scaling (DVS) in 65-nm Energy-Efficient Power Management With Frequency-Based Control (FBC) for SoC System

A 65-nm energy-efficient power management with frequency-based control (FBC) is proposed to achieve the near-optimum dynamic voltage scaling (DVS) in a system-on-chip system. Since DVS and dynamic frequency scaling (DFS) operations are demanded for system processor, control loop of the proposed single-inductor dual-output (SIDO) power module is merged with the frequency-controlled phase-locked loop (PLL) to constitute the operation of hybrid control loop. This means that both DVS and DFS operations can be guaranteed and are not affected by process, supply voltage, and temperature variations. The proposed power management can receive the demand of system processor by hybrid control loop and can help realize the supply voltage with different operation tasks for near-optimum DVS operation. The fabricated chip occupies a 1.12-mm2 silicon area. Experimental results show that the SIDO power module achieves a peak efficiency of 90% and the highest power reduction of 33% with the proposed near-optimum DVS operation.

A 0.003 mm

This paper describes a single-channel, calibration-free Successive-Approximation-Register (SAR) ADC with a resolution of 10 bits at 240 MS/s. A DAC switching technique and an addition-only digital error correction technique based on the non-binary search are proposed to tackle the static and dynamic non-idealities attributed to capacitor mismatch and insufficient DAC settling. The conversion speed is enhanced, and the power and area of the DAC are also reduced by 40% as a result. In addition, a switching scheme lifting the input common mode of the comparator is proposed to further enhance the speed. Moreover, the comparator employs multiple feedback paths for an enhanced regeneration strength to alleviate the metastable problem. Occupying an active area of 0.003 mm 2 and dissipating 0.68 mW from 1 V supply at 240 MS/s in 28 nm CMOS, the proposed design achieves an SNDR of 57 dB with low-frequency inputs and 53 dB at the Nyquist input. This corresponds to a conversion efficiency of 4.8 fJ/c.-s. and 7.8 fJ/c.-s. respectively. The DAC switching technique improves the INL and DNL from +1.15/-1.01 LSB and +0.92/-0.28 LSB to within +0.55/-0.45 LSB and +0.45/-0.23 LSB, respectively. This ADC is at least 80% smaller and 32% more power efficient than reported state-of-the-art ADCs of similar resolutions and Nyquist bandwidths larger than 75 MHz.

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This paper presents and analyzes a fully digital instruction-cycle-based dynamic voltage scaling (iDVS) power management strategy for low-power processor designs. The proposed iDVS technique is fully compatible with conventional DVS scheduler algorithms. An additional computer aided design-based design flow was embedded in a standard cell library to implement the iDVS-based processor in highly integrated system-on-a-chip applications. The lattice asynchronous self-timed control digital low-dropout regulator with swift response and low quiescent current was also utilized to improve iDVS voltage transition response. Results show that the iDVS-based processor with the proposed adaptive instruction cycle control scheme can efficiently perform millions of instructions per second during iDVS transition. The iDVS-based digital signal processor chip was implemented in a HH-NEC 0.18-μm standard complementary metal-oxide semiconductor. Measurement results show that the voltage tracking speed with 11.6 V/μs saved 53% power.

10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching

A 10b 200MS/s folding ADC is implemented with a cascaded folding factor of 4x5 to reduce the number of comparators. A simple offset calibration is developed to avoid the complex calibration loops, improving the settling behavior of the ADC. After calibration, the measured ENL is enhanced from +8M.5LSB to +1.4/-1.5LSB while the SNDR performance is improved from 43.9dB to 54.1dB at input frequency of 10.1MHz. Fabricated in 0.35/0.13 mum CMOS, the ADC occupies an area of 0.45 mm2. The analog and digital circuits dissipate 285mW at 3.3V and lmW at 1.2V power supply, respectively.

Instruction-Cycle-Based Dynamic Voltage Scaling Power Management for Low-Power Digital Signal Processor With 53% Power Savings

The proposed cross-source energy (CSE) harvesting circuit can accept universal energy sources, including AC and DC sources. The buck-boost conversion of CSE harvesting circuit automatically converts AC or DC input into DC output without being limited by universal input voltage range. CSE harvesting circuit provides dual outputs, a regulated output and a battery charging output, to optimally arrange harvest energy with 72.5% of power efficiency. A backup converter is designed to cooperate with CSE harvesting circuit to guarantee voltage stability of the regulated output. The proposed analog iterating-based (AIB) maximum power point tracking (MPPT) technique achieves 94.6% tracking efficiency without complex data calculation and storage compared to previous techniques.

A 10b 200MS/s pipelined folding ADC with offset calibration

Single-inductor multiple-output (SIMO) DC-DC buck converters, which possess the advantage of compact size, are commonly implemented in portable electronics like mobile phones and tablets. However, their power efficiency is degraded considerably, as illustrated in Fig. 12.6.1, when multiple outputs are requested in a wide range, such as 1.2 to 3.3V for tablets. The use of P-MOSFET [1][2] and N-MOSFET [3] switches results in low efficiency of 64 and 70% at outputs of 1.2 and 3.3V, respectively, because of low gate driving voltages and large on-resistance. This implies that conventional usage of P-MOSFET and N-MOSFET switches is inappropriate in SIMO converters [1-3]. This paper presents a SIMO converter with output-independent gate drive (OIGD) control for all N-MOSFET switches. One of the salient features is that OIGD control achieves output-voltage-independent characteristics on efficiency and keeps peak efficiency of 90% over the range of 1.2 to 3.3V for tablets. The other salient feature is that a low-power deadtime overstress recycling (DOR) technique retrieves 95% of energy loss during deadtime and releases the overstress problem simultaneously.

A Direct AC–DC and DC–DC Cross-Source Energy Harvesting Circuit with Analog Iterating-Based MPPT Technique with 72.5% Conversion Efficiency and 94.6% Tracking Efficiency

Lighting flicker, a rapid and repeated change over time in the brightness of light, has long been known to cause illness in humans that ranges from headaches to seizures. Thus, [1] has specified the dimming frequency, fDIM, larger than 3kHz to achieve a no-observable-effect flicker level. State-of-the-art LED drivers employ the SIMO topology with four channels in Fig. 12.7.1, to deliver energy to each LED using the time-multiplexing (TM) control technique [2-4], in which the luminance is controlled by the dimming signals. Two major shortcomings for such approaches are: (1) Sequential dimming signals; and (2) Current cross-regulation (CCR) effects. In [2], the LED drivers with TM control result in only 9b color resolution at the dimming frequency of 1.5kHz, which may cause flicker hazard. Besides, the complete white-red-green-blue (WRGB) sequence needs a total of four switching periods to light up the 4 LEDs separately. On the other hand, due to inherent rising and falling delay of the hysteretic current control (HCC) circuit, tdr and tdf respectively, the CCR effect seriously affects the accuracy of the controller when the inductor current slope is varied. For example, with L=15μH, VIN=20V, VR=2.5V, VG=3.5V, tdr=300ns and tdf=250ns, the SIMO will result in 4% CCR between Iavg,R and Iavg,G when the average LED current is 1A. More specifically, with the same color in the sequence, voltage regulation may be disregarded when regulated constant current through the sensing resistor RSEN is used as a negative feedback control. However, when different colors are in sequence, where VO, =VR, VG, VB, or VW, are different, large voltage cross-regulation (VCR) across the RSEN occurs and so does the CCR. The CCR effects become an open question for enhancing LED current accuracy. For alleviating the CCR effect, the discontinuous conduction mode (DCM) has been applied for TM control in [3]. However, with the limited output current in DCM, low output power resulted and large output capacitors were required to suppress the VCR. In this paper, a single-inductor multiple-floating-output (SIMFO) LED driver with an average-current-correction (ACC) technique is presented. The developed ACC technique is used to alleviate the CCR effect to about 0.5%. The developed LED driver using the floating output topology offers the following salient features: (1) A complete WRGB sequence is operated in only one switching cycle; (2) All LEDs can be dimmed simultaneously and each LED can also be dimmed individually to achieve 24b color resolution at fDIM=3kHz without flicker hazard; and (3) Achieving high output power and power efficiency (96%).

12.6 90% Peak efficiency single-inductor-multiple-output DC-DC buck converter with output independent gate drive control

The magnetic energy harvesting (MEH) circuit and the power monitoring system are proposed in this paper to enlarge the system sustainability on wireless sensing or the monitoring system. The proposed MEH circuit harvests magnetic power on power wires through a power sensing current transformer (CT) and charges power monitoring system. The MEH circuit includes the direct ac-dc rectifier and the maximum power extracting (MPE) control circuit. The direct ac-dc rectifier can directly rectify ac input to the dc output current. The proposed MPE control fits the characteristic of magnetic energy source compared to the conventional resistor emulation maximum power point tracking method. Owing to continuous tracking the maximum power of the CT, 120% harvesting power improvement can be achieved under the same CTs sensing current. Peak efficiency of 82% can be achieved under the sensing current of 8 A. The test chip is fabricated in 0.25 μm CMOS process with an active area of 0.98 mm2.