Ying-Hsi Lin

An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration

An 11 b 800MS/S time-interleaved ADC is implemented in a 90nm CMOS process for a 10GBase-T application. A single open-loop T/H circuit using a cascode source follower achieves high resolution and conversion rate. The offset and gain mismatches are corrected by the digital background calibration. The measured DNL and INL are <0.5LSB and <1.6LSB, respectively. The measured SNDRs are 58 and 54dB for 15 and 400MHz inputs, respectively. The 1.4mm2 ADC consumes 350mW from a 1.3V supply (1.5V for T/H).

A 2.4-GHz +25dBm P-1dB linear power amplifier with dynamic bias control in a 65-nm CMOS process

A 2.4 GHz linear CMOS power amplifier (PA) for OFDM WLAN application in 65 nm CMOS technology is presented. The cascode PA operating from 3.3 V employs the proposed asymmetric lightly doped drain MOSFET (A-LDD) structure as common-gate stage to sustain large signal stress and 1.2 V core device as common source stage to provide high frequency operation. Beside, dynamic bias technique is used not only to increase efficiency but also improve the linearity. In the measurement, the breakdown voltage of the A-LDD MOSFET can achieve 6.2 V compared to standard I/O device of 5 V. A PA EVM of -29 dB is achieved at output power of 17 dBm with DC current of 173 mA from 3.3 V supply. Also, it reveals the output P1 dB of PA is 25.3 dBm.

A DVS embedded power management for high efficiency integrated SOC in UWB system

The proposed power management module with a typical 1.2 V low-voltage PWM (LV-PWM) controller and dynamic voltage scaling (DVS) function is designed using 65 nm technology for integration with the ultra-wide band (UWB) system. The on-chip pre-regulator with a power conditioning circuit can provide a regulated supply voltage to the LV-controller. Moreover, the proposed handover technique can achieve the self-biasing mechanism to further reduce power dissipation. To operate in low voltage, the proposed compensation enhancement multistage amplifier (CEMA) can achieve high loop gain and ensure system stability without using any external compensation component. The fabricated power management module occupies 0.356 mm2 silicon area with an excellent line/load transient response. Owing to the DVS function, the proposed power management can meet the power requirement in the UWB system and other RF transceiver systems.

A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement

A low quiescent current asynchronous digital- LDO (D-LDO) regulator integrated with a phase-locked loop (PLL)-modulated switching regulator (SWR) that achieves the near-optimum power management supply for core processor in system-on-chip (SoC). The parallel connection of the asynchronous D-LDO regulator and the ripple-based control SWR can accomplish fast-DVS (F-DVS) operation as well as high power conversion efficiency. The asynchronous D-LDO regulator controlled by bidirectional asynchronous wave pipeline realizes the F-DVS operation, which guarantees high million instructions per second (MIPS) performance of the core processor under distinct tasks. The use of a ripple-based control SWR operating with a leading phase amplifier ensures fast response and stable operation without the need for large equivalent-series-resistance, thus reducing the output voltage ripple for the enhancement of supply quality. The fabricated chip occupies 1.04 mm2 in 40 nm CMOS technology. Experimental results show that a 94% peak efficiency with a voltage tracking speed of 7.5 V/μs as well as the improved MIPS performance by 5.6 times was achieved.

Minimized Transient and Steady-State Cross Regulation in 55-nm CMOS Single-Inductor Dual-Output (SIDO) Step-Down DC-DC Converter

A single-inductor dual-output (SIDO) step-down DC-DC converter with continuous conduction mode (CCM) operation is proposed to achieve an area-efficient power management module. The low-voltage energy distribution controller (LV-EDC) can simultaneously guarantee good voltage regulation and low output voltage ripple. With the proposed dual-mode energy delivery methodology, cross regulation in steady-state output voltage ripple, which is rarely discussed, and cross regulation in load transient response are both effectively reduced. In addition, the energy mode transition operation helps obtain the appropriate energy operation mode using the energy delivery paths for dual outputs. Moreover, within the allowable output voltage ripple, the automatic energy bypass (AEB) mechanism can reduce the number of energy delivery paths, thereby ensuring voltage regulation and further enhancing efficiency. The test chip, fabricated in 55-nm CMOS, occupies 1.44 mm2 and achieves 91% peak efficiency, low output voltage ripple, and excellent load transient response for a high-efficiency system-on-a-chip (SoC) integration.

A Low-Power Fullband 802.11a/b/g WLAN Transceiver With On-Chip PA

A low-power fullband 802.11a/b/g WLAN transceiver in 0.15-mum CMOS technology is described. The zero-IF transceiver achieves a receiver noise figure of 4.4/4 dB for the 2.4-GHz/5-GHz bands, respectively. The corresponding sensitivity at 54-Mb/s operation is -72 dBm for 802.11g and -74 dBm for 802.11a using actual PER measurement. An on-chip PA delivers 20 dBm output P1-dB. A new I/Q compensation scheme is implemented in local oscillator (LO) and an image rejection of better than 52 dB is observed. The transmitter delivers 10/1.5 dBm (2.4-/5-GHz) EVM-compliant output power for a 64-QAM OFDM signal at 54-Mb/s. The power consumption is 117/135 mW (1.8-V) in the receive mode and 570/233.1 mW in the transmit mode for 2.4/5 GHz, respectively. The low power consumption, high integration and robustness (-40 to 140degC) make this transceiver suitable for portable applications

A Battery-Free 217 nW Static Control Power Buck Converter for Wireless RF Energy Harvesting With

A battery-free nano-power buck converter with a proposed dynamic on/off time (DOOT) control can achieve high conversion efficiency over a wide load range. The DOOT control can predict the on/off time at different input voltages without a power consuming zero current detection (ZCD) circuit, as well as suppress static power in idle periods. To adapt to the fluctuations in a harvesting system, the proposed α-calibration scheme guarantees accurate ZCD over process, voltage variation, and temperature (PVT) in the DOOT to improve power conversion efficiency. Furthermore, the adaptive phase lead (APL) mechanism can improve inherent propagation delay attributable to low-power and non-ideal comparator, thus improving load regulation by a maximum of 30 mV. The test chip was implemented in 0.25-μm CMOS process with a die area of 0.39 mm2. Experimental results showed 95% peak efficiency, low static power of 217 nW and good load regulation of 0.1 mV/mA, which are suitable for RF energy harvesting applications.

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A time-interleaved pipeline ADC is designed with the reconfigurable resolution and sampling rate, Fs, to accommodate different operation scenarios. The main offset and gain mismatches between four sub-ADCs are modulated to the frequency of F/2 by the reference-and opamp-sharing techniques. Fabricated in 90 nm CMOS, the 7 bit ADC has an ENOB of 6.5 at 1.1 GHz sampling rate. The I/Q ADCs totally consume power of 92 mW from a 1.3 V supply.

-Calibrated Dynamic On/Off Time and Adaptive Phase Lead Control

A 2.4/5GHz Fully-Integrated Transceiver is implemented in 65nm CMOS technology. To alleviate the cost of external front-end components, the G-mode RF transmit/receive (T/R) switch and a power-efficient linear CMOS PA are fully integrated on-chip. On the other hand, for better performance, only the A-mode PA is integrated on-chip while the external T/R switch is used. It shows 5dB and 5.5dB NF in the G-mode and A-mode receivers respectively. Also, the transmitter delivers an average power of 18dBm OFDM (64QAM, 54MBPS) signal with EVM of -28dB for G-mode application and 16dBm OFDM (64QAM, 54MBPS) signal with EVM of −28dB for A-mode application after digital pre-distortion.

A 7b 1.1GS/s Reconfigurable Time-Interleaved ADC in 90nm CMOS

A 65-nm energy-efficient power management with frequency-based control (FBC) is proposed to achieve the near-optimum dynamic voltage scaling (DVS) in a system-on-chip system. Since DVS and dynamic frequency scaling (DFS) operations are demanded for system processor, control loop of the proposed single-inductor dual-output (SIDO) power module is merged with the frequency-controlled phase-locked loop (PLL) to constitute the operation of hybrid control loop. This means that both DVS and DFS operations can be guaranteed and are not affected by process, supply voltage, and temperature variations. The proposed power management can receive the demand of system processor by hybrid control loop and can help realize the supply voltage with different operation tasks for near-optimum DVS operation. The fabricated chip occupies a 1.12-mm2 silicon area. Experimental results show that the SIDO power module achieves a peak efficiency of 90% and the highest power reduction of 33% with the proposed near-optimum DVS operation.