Chaoqi Zhang

Highly Elastic Gold Passivated Mechanically Flexible Interconnects

A wafer-level batch fabricated mechanically flexible interconnect (MFI) technology with 65- μm vertical elastic range of motion is experimentally demonstrated. A metal alloy (NiW) with ultrahigh yield strength and enhanced geometrical design is adopted to enable elastic deformation over the entire vertical range of motion. The enhanced geometrical design of the MFIs ensures that the stress is distributed uniformly during deformation, and simultaneously maintains an inner stress that is lower than the yield strength of NiW during vertical deformation. In addition, the MFIs are passivated with gold, which is experimentally verified to not only lower the electrical resistance, but also significantly extends the lifetime of the MFIs as it eliminates oxidation of NiW. For 10- μm-thick Au-NiW MFIs, the contact force is up to 10 mN at 50- μm elastic vertical deformation (i.e., compliance of 5 mm/N).

Thermal Isolation Using Air Gap and Mechanically Flexible Interconnects for Heterogeneous 3-D ICs

This paper presents a set of thermal isolation technologies to provide a measure to thermally insulate low-power temperature-sensitive tiers from the time-varying power dissipation of high-power tier in heterogeneous 3-D integrated circuits. The proposed technologies use an air gap and mechanically flexible interconnects (MFIs) to replace conventional microbumps and underfill. A two-tier testbed is fabricated to emulate a heterogeneous 3-D stack. The results are then benchmarked with a standard 3-D stacking approach that is simulated using finite-volume modeling. Compared with the conventional approach using microbumps and underfill, a temperature reduction of 35.9% can be achieved in the low-power tier by implementing the air gap and MFIs. Four-point and daisy-chain resistances of the MFIs are measured to verify the electrical connectivity between the tiers during temperature cycling.

Self-Aligned Silicon Interposer Tiles and Silicon Bridges Using Positive Self-Alignment Structures and Rematable Mechanically Flexible Interconnects

A novel large-scale silicon system platform is proposed and demonstrated. In this paper, three silicon interposer tiles are aligned and mounted on a printed wiring board (PWB), and two silicon bridges are aligned and mounted on top of the three interposer tiles; each silicon bridge spans two interposer tiles. Four positive self-alignment structures and four inverted pyramid pits self-align a tile to the PWB and a bridge to two tiles. Mechanically flexible interconnects (MFI) form nonbonding electrical connections between the three interposer tiles and two silicon bridges; MFIs are fabricated on the interposer tiles. Pointy tips on the MFIs form low contact resistance with the pads on the silicon bridges. Less than 4 μm alignment error is demonstrated on a stack of silicon substrates, and <;8μm alignment error between a silicon bridge and tiles is also demonstrated on a FR4 substrate. Daisy chain and four-point measurements are performed to verify electrical connections between the three interposer tiles via MFIs and silicon bridges.

Interposer-to-interposer electrical and silicon photonic interconnection platform using silicon bridge

Developing solutions that provide high-bandwidth and low-energy communication has been at the forefront of interconnect and packaging research [1]. Within a module, the challenge has been addressed by using novel 2.5D (silicon interposer) and 3D stacking for short and high-density electrical interconnections and silicon photonics based interconnects. However, wafer-level batch fabricated solutions for high-bandwidth and low-energy interconnection between modules remain largely missing. Fig. 1 illustrates three approaches for package-to-package communication: through the motherboard, Flex connection [2], and using optical fibers. Electrical connectivity through the motherboard is both bandwidth limited and energy consuming. The use of Flex connection provides lower loss channels, however it requires a serial assembly process, which may limit its scalability. Methods involving optical fibers suffer the same limitation and are limited to relatively large interconnect pitches.

Gold passivated mechanically flexible interconnects (MFIs) with high elastic deformation

This paper reports the fabrication and testing of gold passivated mechanically flexible interconnects (MFIs) with elastic deformation of 65 μm. It is shown that the gold passivation plays a critical role in preserving the lifetime of the flexible interconnects. The gold-passivated MFIs exhibit an unchanged force-displacement characteristic after being vertically indented 100 cycles.

Mechanically flexible interconnects (MFIs) with highly scalable pitch

Mechanically flexible interconnects (MFIs) with highly scalable pitch (from 150 to 50 µm) and large vertical gap (65 µm) are reported for the first time in this paper. The wafer-level batch fabrication of the reported MFIs is enabled by photolithography on a highly non-uniform surface (65 µm high sacrificial domes) covered with a spray-coated photoresist. Based on finite element method simulations and experimental data, the mechanical compliance and resistance of the fabricated MFIs are reported.

Self-alignment structures for heterogeneous 3D integration

A novel self-alignment technology, called positive self-alignment structures (PSAS), for heterogeneous 3D integration is described. Using a set of precisely reflowed photoresist structures in conjunction with the corresponding inverse pyramid pits, we demonstrate that submicron alignment can be achieved without an advanced placement tool. The positive self-alignment structure technology is fabricated on top of electronics or devices, and as a result, it does not take up additional electronic real estate, and it can be fabricated on any surface, including glass. This enables heterogeneous integration that involves non-silicon substrates, and at the same time simplifies the stacking of three or more chips. This paper describes the self-alignment mechanism, the fabrication of positive self-alignment structures (PSAS), and the test structures to measure the accuracy of alignment; the resulting misalignment on various substrates including glass and unpolished silicon surfaces are reported. In addition, the stacking of five chips is demonstrated and the resulting misalignment at each of the chip-to-chip interfaces is measured and reported.

Fabrication of and cell growth on ‘silicon membranes’ with high density TSVs for bio-sensing applications

A silicon membrane acting as an interface layer between live cells and the sensing electronics enabling low-cost, high-throughput bio-sensing is proposed; the interface is capable of supporting high pixel density allowing accurate image mapping. Cell attachment and growth was carried out on five different silicon based surfaces and compared to the standard Tissue Culture Polystyrene (TCPS) surface in order to optimize the selection process of the interface material; cell imaging is performed after 48 hours to study the effect of different surface variations (different materials on silicon, presence of metal, increased surface roughness due to CMP, etc.) on cell adhesion and growth. The results show that cells successfully adhere and grow onto the sensing electrodes for all the surfaces under test after the first 48 hours. Key enabling technologies for high pixel density membranes are also presented.

Au-NiW Mechanically Flexible Interconnects (MFIs) and TSV integration for 3D interconnects

Mechanically Flexible Interconnects (MFIs) with a pitch of 50 μm and a standoff height of 65 μm are reported. Mechanical characterization of the MFIs using indentation demonstrates elastic deformation and the feasibility of temporary interconnection. The integration of MFIs and TSVs is also reported along with electrical testing for interposer and 3D IC applications.

Revolutionary Innovation in System Interconnection: A New Era for the IC

This paper describes novel microscale electrical, optical, and fluidic interconnect networks to address off-chip interconnect challenges in high-performance computing systems as well as to enable 3D heterogeneous integration of CMOS and MEMS/sensors.