Muneeb Zia

Thermal Isolation Using Air Gap and Mechanically Flexible Interconnects for Heterogeneous 3-D ICs

This paper presents a set of thermal isolation technologies to provide a measure to thermally insulate low-power temperature-sensitive tiers from the time-varying power dissipation of high-power tier in heterogeneous 3-D integrated circuits. The proposed technologies use an air gap and mechanically flexible interconnects (MFIs) to replace conventional microbumps and underfill. A two-tier testbed is fabricated to emulate a heterogeneous 3-D stack. The results are then benchmarked with a standard 3-D stacking approach that is simulated using finite-volume modeling. Compared with the conventional approach using microbumps and underfill, a temperature reduction of 35.9% can be achieved in the low-power tier by implementing the air gap and MFIs. Four-point and daisy-chain resistances of the MFIs are measured to verify the electrical connectivity between the tiers during temperature cycling.

Interposer-to-interposer electrical and silicon photonic interconnection platform using silicon bridge

Developing solutions that provide high-bandwidth and low-energy communication has been at the forefront of interconnect and packaging research [1]. Within a module, the challenge has been addressed by using novel 2.5D (silicon interposer) and 3D stacking for short and high-density electrical interconnections and silicon photonics based interconnects. However, wafer-level batch fabricated solutions for high-bandwidth and low-energy interconnection between modules remain largely missing. Fig. 1 illustrates three approaches for package-to-package communication: through the motherboard, Flex connection [2], and using optical fibers. Electrical connectivity through the motherboard is both bandwidth limited and energy consuming. The use of Flex connection provides lower loss channels, however it requires a serial assembly process, which may limit its scalability. Methods involving optical fibers suffer the same limitation and are limited to relatively large interconnect pitches.

A Memory-Based Logic Block With Optimized-for-Read SRAM for Energy-Efficient Reconfigurable Computing Fabric

A memory-based logic block (MLB), which is a building block for memory-based reconfigurable computing framework, is presented in 130-nm CMOS. The MLB is designed with an optimized-for-read (OFR) 6T static random access memory (SRAM)-based lookup table and demonstrates single- and multicycle evaluation of complex functions. Power-aware mapping leverages the data-dependent read power of the OFR SRAM to reduce MLB evaluation power.

Fabrication of and cell growth on ‘silicon membranes’ with high density TSVs for bio-sensing applications

A silicon membrane acting as an interface layer between live cells and the sensing electronics enabling low-cost, high-throughput bio-sensing is proposed; the interface is capable of supporting high pixel density allowing accurate image mapping. Cell attachment and growth was carried out on five different silicon based surfaces and compared to the standard Tissue Culture Polystyrene (TCPS) surface in order to optimize the selection process of the interface material; cell imaging is performed after 48 hours to study the effect of different surface variations (different materials on silicon, presence of metal, increased surface roughness due to CMP, etc.) on cell adhesion and growth. The results show that cells successfully adhere and grow onto the sensing electrodes for all the surfaces under test after the first 48 hours. Key enabling technologies for high pixel density membranes are also presented.

Au-NiW Mechanically Flexible Interconnects (MFIs) and TSV integration for 3D interconnects

Mechanically Flexible Interconnects (MFIs) with a pitch of 50 μm and a standoff height of 65 μm are reported. Mechanical characterization of the MFIs using indentation demonstrates elastic deformation and the feasibility of temporary interconnection. The integration of MFIs and TSVs is also reported along with electrical testing for interposer and 3D IC applications.

3-D Integrated Electronic Microplate Platform for Low-Cost Repeatable Biosensing Applications

This paper presents a 3-D integrated disposable “electronic microplate” (e-microplate) platform that allows the reuse of CMOS biosensor, thereby significantly reducing cost and increasing throughput compared to nondisposable biosensing systems. The e-microplate utilizes mechanically flexible interconnects and through-silicon-vias to electrically connect the cells cultured on the top (sensing electrode side) of the e-microplate to the electrodes on the CMOS biosensor while maintaining a physical separation between the aforementioned substrate tiers. Electrical measurements performed show that the incorporation of the e-microplate does not degrade the sensing amplifiers gain, 3-dB bandwidth, or the input referred noise; this ensures a high signal-to-noise ratio allowing accurate sensing of weak signals from living cells under test. Cell growth experiments performed show adhesion and growth of mouse embryonic stem cells on the surface of the sensing electrodes of the e-microplate. Impedance mapping for Dulbeccos phosphate buffered saline solution performed with the e-microplate, for two different e-microplate assemblies, confirms the functional accuracy of the assembled systems.

Dense and Highly Elastic Compressible MicroInterconnects (CMIs) for Electronic Microsystems

In this paper, dense, highly elastic compressible microinterconnects (CMIs) are presented as an enabling technology for next generation sockets, probe cards and heterogeneous integrated systems. Free-standing CMIs with 75 µm height are fabricated using a thick sacrificial photoresist layer with an upward curved sidewall profile. The CMIs show a 45 µm vertical elastic range of motion. The fabricated CMIs have an in-line pitch of 150 µm, mechanical compliance of 9.2 mm/N, and vertical elastic motion of up to 5,000 indentation cycles. The smallest in-line pitch of CMIs demonstrated is 40 µm. The average post-assembly resistance of the CMIs, including the contact resistance, was measured to be 176.3 mΩ.

Electrical and photonic off-chip interconnection and system integration

The ever increasing demand of bandwidth density at low energy budgets has motivated innovations in 2.5D and 3D integration. However, a comprehensive solution allowing electrical and photonic interconnection for short and long-range interconnects remains largely missing. Furthermore, thermal coupling between stacked chips remains a critical bottleneck before leveraging the true potential of 3D integration. Addressing some of these challenges, a large-scale interconnected system using a silicon bridging concept with optical and electrical I/Os which allows the coexistence of electrical and photonic interconnects, and a unique thermal isolation scheme for 3D integrated systems are discussed.

Numerical and experimental exploration of thermal isolation in 3D systems using air gap and mechanically flexible interconnects

This paper proposes a thermal isolation technology using air gap and mechanically flexible interconnects (MFIs) for heterogeneous 3-D integration. Thermal modeling shows that the proposed architecture achieves a temperature reduction of approximately 40.0% in the low-power tier compared to conventional approaches using microbumps and underfill. To demonstrate the technology, a two-tier testbed is fabricated, assembled and tested. The experimental results of test cases show an average temperature reduction of approximately 30.0% in the low-power tier.

Chip-to-chip interconnect integration technologies

With continuous increase in the off-chip bandwidth requirements, conventional interconnection methodologies are quickly becoming incapable of meeting the demand. Recent progress in silicon interposer and 3D integration technologies seek to alleviate some of these bottlenecks. This paper reviews the evolution of conventional interconnect methodologies and recent progress in platforms allowing high-bandwidth low-energy chip-tochip communication.