Charles Ching-Hsiang Hsu

Addressable failure site test structures (AFS-TS) for CMOS processes: Design guidelines, fault simulation, and implementation

As technologies scale down, semiconductor manufacturing processes require more and more areas for test structures to ensure accurate yield estimation. This paper presents design guidelines for test structures with addressable failure sites to efficiently utilize a given area. Different types of test structures with three-level interconnects are developed and validated using a novel simulation system. Based on the proposed algorithm, single and multiple defects can be detected and identified precisely without ambiguity. The methodology standardizes the design of test structures for defect capturing as well as their usage within a common pad frame, which can be shared for various processes and applications. A test chip of 22/spl times/6.6 mm/sup 2/ containing a variety of types of these test structures was implemented to demonstrate the design feasibility.

Design and simulation of addressable failure site test structure for IC process control monitor

A novel test structure to ensure failure addressable and high-density test structure of semiconductor process control monitor with a limited number of contact pads required for electrical test is described. The placement and routing scheme requires only two levels of conductive layers, and provides the maximum number of bridging and continuity test structure units. A graph model is developed to manifest the spatial configuration of test structure units and simplify the complexity of fault detection. Also, a generic algorithm of multi-fault detection was developed.

The short-loop process tuning & yield evaluation by using the addressable failure site test structures (AFS-TS)

This work describes the implementation of a novel test structure called addressable failure site test structure (AFS-TS) for via process optimization including the liner layer and W-CVD filling process. It manifests the design, defect detection and yield analysis of addressable failure site test structures. The novel test structures are used to discriminate the yield loss issues based on the high spatial defect detection resolution within 2000/spl times/2200 /spl mu/m/sup 2/ of interconnect test structures. A test chip of 4.0/spl times/6.6 mm/sup 2/ containing nine types of test structures was implemented using 0.25 /spl mu/m logic backend of line process. This simple and efficient killer defect identification of process steps is employed as yield enhancement strategy.

Novel assessment of process control monitor in advanced semiconductor manufacturing: a complete set of addressable failure site test structures (AFS-TS)

This work describes the implementation of a novel assessment of process control monitor in advanced semiconductor manufacturing. It manifests the design and simulation results of addressable failure site test structures. Four novel test structures with three level interconnects have been developed and validated with an in-house simulation system. The novel test structures are used to identify the locations of killer defects. A test chip of 22/spl times/6.6 mm/sup 2/ containing four types test structures was implemented using a 0.25 /spl mu/m logic backend of line process. This simple and efficient test structure for killer defect identification demonstrated its superiority in yield enhancement.

Quantum size effects on photoluminescence from Si nanocrystals in PECVD silicon-rich-oxide

Red-shift of photoluminescence (PL) spectra and increasing intensity after subsequent annealing have been observed in plasma-enhanced chemical-vapor-deposition (PECVD) silicon-rich-oxide (SRO). Based on FTIR results, however, PECVD SRO does experience chemical and structural changes during post-deposition annealing and becomes denser. Besides, the enhanced tunneling characteristics of MOS capacitor using SRO thin film as injector due to nanocrystalline silicon (nc-Si) in SRO thin film is also observed. These results strongly suggest the luminescence and the enhanced tunneling characteristics originate from the quantum size effect of nc-Si. In this paper, a Si-island model is proposed to delineate the gradual red-shift phenomenon of PL spectra.

Direct observation of channel-doping-dependent reverse short channel effect using decoupled C-V technique

A non-destructive high resolution Decoupled C-V Technique for small geometry devices has been developed and demonstrated to successfully extract the intrinsic channel capacitance of submicron metal-oxide-semiconductor field effect transistors (MOSFETs). The effective channel doping concentration calculated from the extracted intrinsic gate capacitance presents an obvious dopant concentration enhancement in the intrinsic channel region of submicron devices compared to that of long channel devices, as the channel implant dose increases beyond a critical value. The anomalous reverse short channel effect i.e. threshold voltage increases with channel length scaled down, is simultaneously observed on the heavily doped short channel devices. The self-consistency between the C-V and I-V measurement supports that the reverse short channel effect apparent in the submicron CMOS technology is due to the channel dopant enhancement induced by high dose channel implants for both N-channel and P-channel devices.

Effective Channel Length and Source-Drain Series-Resistance Determination after Electrical Gate Length Verification of Metal-Oxide-Semiconductor Field-Effect Transistor

A new technique of determining the effective channel length by directly measuring source-drain series resistance of metal-oxide-semiconductor field-effect transistors (MOSFETs) was proposed. By using MOSFETs with scaled gate lengths, the source-drain series resistance can be obtained from a device whose source and drain regions are connected. In order to determine whether a MOSFETs source and drain are connected, a `difference of total resistance (DTR) method, which can also be used to electrically determine the gate length of a normal MOSFET after the fabrication process, was developed in this study. The effective channel length can then be extracted from the obtained series resistance and I–V of MOSFETs. This technique, although it requires very short-gate-length devices, is not affected by source-drain series-resistance gate bias dependence issue encountered in conventional I–V methods.

Defect detection for short-loop process and SRAM-cell optimization by using addressable failure site-test structures (AFS-TS)

This work describes the utilization of a novel test structure called addressable failure site test structure for short-loop defect detection and proposed a prototype test structure for SRAM process defect detection in advanced semiconductor manufacturing. The novel test structures are used to identify the locations of killer defects which are then used to wafer map defect sites. This simple and efficient killer defect identification of process steps is employed as yield enhancement strategy.

Mechanism and annihilation of shallow-trench-isolation-enhanced poly-mask-edge N + /P-well junction leakage

The dislocation at the trench corner under Poly mask edges was found to be the major killer of junction leakage in generic logic technology. The impact of the sacrificial oxide (SAC-OX) of the well ion implantation (I/I) module and the source/drain (S/D) I/I to the defect formation are investigated for the first time. The influence on N+/P-Well junction leakage caused by the I/I sacrificial oxide from the Rapid Thermal Oxidation (RTO) and Furnace Oxidation (FO) are evaluated by using the process monitoring test structures. Based on the analysis of test structures and the yield evaluation of product, the optimized condition is proposed.

Optimization of low-k dielectric (fluorinated SiO/sub 2/) process and evaluation of yield impact by using BEOL test structures

This work describes the optimization of low-k dielectric process and evaluation of yield impact by using back end of line (BEOL) test structures. Three splits of the low-k dielectric process were compared with high-density-plasma un-doped-silicon-glass (HDP-USG) process and are electrically characterized with the test structures of the BEOL unit process and integration process parameter extraction. The interconnect capacitance is used as the optimization criteria of low-k dielectric process and the yield impact is reviewed for the concern of manufacturing.