K.L. Young

Field-Configurable Test Structure Array (FC-TSA): Enabling Design for Monitor, Model, and Manufacturability

This work is designated to provide a common frame work of test chip design for technology development and process routine monitor, called as field-configurable test structure array (FC-TSA), which can accommodate and test the various types of test structures including transistors, diodes, and resistors. To minimize the probe-pad number and fully utilize area to maximize the area design efficiency, the memory addressing design scheme is implemented to select the device-under-test in a test chip. With the aid of using adjustable channel width of transmission gates, the input resistance of FC-TSA cell can be parameterized and configured to match with the parasitic resistance of various test structures, moreover, the background leakage could be minimized to meet with 1nA design specification. Two types of array test structures, 12/spl times/25 and 40/spl times/25, are implemented with generic logic process to demonstrate the design feasibility. The measurements of transistor set and process monitor test structures are reviewed and corresponding models are discussed.

LOGIC product yield analysis by Wafer Bin Map pattern recognition supervised neural network

AbstracI -Wafer Bin Maps (WBMs) are important for yield improvement to trace root causes. The characteristic of WBMs patterns are formed by processes, so process engineers can collect clues from the patterns and correlate them with speciJic processes. and this can save much time and eforts in finding the root causes. However, the existing learning algorithms have the main shortage of product dependency. For this reason, this work adopted a supervised learning methodology to develop an on-line WBMs pattern recognition system that maps WBMs into 70x70 binary images to salve this issue. Furthermore, this work also proposed a learning scheme to recognize repeating failures that are usually viewed as random pattern in the existing approaches.

A novel array-based test methodology for local process variation monitoring

As process technologies continually advance, local process variation has greatly increased and gradually become one of the most critical factors for integrated circuit manufacturing. To monitor local process variation, a large number of devices-under-test (DUTs) in close proximity must be measured. In this paper, we present a novel array-based test structure to characterize local process variation with limited area overhead. The proposed test structure can guarantee high measurement accuracy by application of the test techniques proposed in this paper: hardware IR compensation, voltage bias elevation, and leakage-current cancelation. Furthermore, the DUT layout need not be modified for the proposed test structure. Thus, the measured variation exactly reflects the reality in the manufacturing environment. The measured results from the few most advanced process-technology nodes demonstrate the effectiveness and efficiency of the proposed test structure in quantifying local process variation.

Electrical characterization of model-based dummy feature insertion in Cu interconnects

A methodology is proposed to characterize the electrical performance of model-based dummy feature insertion in Cu interconnect. Two types of test structures were designed to explore the electrical performance discrepancy between the rule-based and model-based dummy feature insertion. The sheet resistance dependency on design rule is characterized at the various density conditions. 2-D field solver extracts the parasitic capacitance caused by dummy feature insertion. A model-based dummy feature insertion algorithm using randomized shapes is proposed to assist the uniformity control of Cu CMP and MIT/SEMATECH 854 AZ test vehicle is used to demonstrate the feasibility of the proposed algorithm.

A Novel Array-Based Test Methodology for Local Process Variation Monitoring

As process technologies continually advance, local process variation has greatly increased and gradually become one of the most critical factors for IC manufacturing. To monitor local process variation, a large number of DUTs (device-under-test) in close proximity must be measured. In this paper, we presents a novel array-based test structure to characterize local process variation with limited area overhead. The proposed test structure can guarantee high measurement accuracy by utilizing the proposed hardware IR compensation and voltage bias elevation. Furthermore, the DUT layout need not be modified for the proposed test structure so that the measured variation exactly reflects the reality in the manufacturing environment. The measured results from the few most advanced process-technology nodes demonstrate the effectiveness and efficiency of the proposed test structure in quantifying local process variation.

Library-based process test vehicle design framework

This work describes a test vehicle design framework, which minimizes the discrepancy among design rule set, tests structure design and testing plan. The framework is composed of the symbolic design rule set, Parametereized-Device, test structure generator, and test vehicle generator. An approach for simplification and consolidation of test structure is proposed to derive the concise test structure library. Finally, implementation of test vehicle is presented.

Design and integration of electrical-based dimensional process-window checking infrastructure

The purpose of this work is to provide a design infrastructure for electrical-based dimensional process-window checking. With the aid of the novel test vehicle design platform, the discrepancy among design rule set, test structure design and testing plan can be minimized. Using the function-independent Test Structure Design Intellectual Properties (TSD-IP) provided by this infrastructure, the process-window could be quantified as the electrical testing of test structures. A cross-generation (130 nm-90 nm) test vehicle which focuses on the evaluation of overlay and critical dimension variation across the intra- and inter-photo field is enacted to demonstrate the design framework.

Defect detection for short-loop process and SRAM-cell optimization by using addressable failure site-test structures (AFS-TS)

This work describes the utilization of a novel test structure called addressable failure site test structure for short-loop defect detection and proposed a prototype test structure for SRAM process defect detection in advanced semiconductor manufacturing. The novel test structures are used to identify the locations of killer defects which are then used to wafer map defect sites. This simple and efficient killer defect identification of process steps is employed as yield enhancement strategy.

Global pattern density effects on low-k trench CDs for sub-65-nm technology nodes

Comprehensive CD characterization of low-k trench etch for 65nm nodes are performed through a specially designed mask with global pattern density (GPD) in the range from 25% to 60%. Unlike traditional means, through this mask we systematically demonstrate global pattern density effects on etch behaviors in correlation with CD uniformity, CD proximity, and CD linearity without local etch loading effect contributed from nearby environment [1-3] and position dependent effect contributed from resist developing or aberrations of the wafer-imaging lens [4]. From our study, CD proximity is the most sensitive item. Wider trench shows larger CD variation as compared with narrow trench when global environment vary. Moreover, we find that low pressure etch conditions in a small chamber volume etcher exhibits less CD variation of global pattern density effect. On the other hand, pressure in a large chamber volume etcher provides better tuning capability in the adjustment of CD variation. The results suggest that residence time might be an influential factor for the GPD dependent CD control.

An assessment of physical and electrical design rule based statistical process monitoring and modeling (PEDR-SPMM): for foundry manufacturing line of multiple-product mixed-run

A novel methodology of physical and electrical design rule based statistical process monitoring and modeling (PEDR-SPMM) was proposed. By the aid of principal component analysis, the correlated physical and electrical parameters are decomposed into an independent variable set. The key parameters of multiple products mixed-run could be formulated by the independent variable set, which reduce the modeling complexity, and also provide a way to get a comparison between different technology nodes.