Sunnys Hsieh

Field-Configurable Test Structure Array (FC-TSA): Enabling Design for Monitor, Model, and Manufacturability

This work is designated to provide a common frame work of test chip design for technology development and process routine monitor, called as field-configurable test structure array (FC-TSA), which can accommodate and test the various types of test structures including transistors, diodes, and resistors. To minimize the probe-pad number and fully utilize area to maximize the area design efficiency, the memory addressing design scheme is implemented to select the device-under-test in a test chip. With the aid of using adjustable channel width of transmission gates, the input resistance of FC-TSA cell can be parameterized and configured to match with the parasitic resistance of various test structures, moreover, the background leakage could be minimized to meet with 1nA design specification. Two types of array test structures, 12/spl times/25 and 40/spl times/25, are implemented with generic logic process to demonstrate the design feasibility. The measurements of transistor set and process monitor test structures are reviewed and corresponding models are discussed.

Addressable failure site test structures (AFS-TS) for CMOS processes: Design guidelines, fault simulation, and implementation

As technologies scale down, semiconductor manufacturing processes require more and more areas for test structures to ensure accurate yield estimation. This paper presents design guidelines for test structures with addressable failure sites to efficiently utilize a given area. Different types of test structures with three-level interconnects are developed and validated using a novel simulation system. Based on the proposed algorithm, single and multiple defects can be detected and identified precisely without ambiguity. The methodology standardizes the design of test structures for defect capturing as well as their usage within a common pad frame, which can be shared for various processes and applications. A test chip of 22/spl times/6.6 mm/sup 2/ containing a variety of types of these test structures was implemented to demonstrate the design feasibility.

The short-loop process tuning & yield evaluation by using the addressable failure site test structures (AFS-TS)

This work describes the implementation of a novel test structure called addressable failure site test structure (AFS-TS) for via process optimization including the liner layer and W-CVD filling process. It manifests the design, defect detection and yield analysis of addressable failure site test structures. The novel test structures are used to discriminate the yield loss issues based on the high spatial defect detection resolution within 2000/spl times/2200 /spl mu/m/sup 2/ of interconnect test structures. A test chip of 4.0/spl times/6.6 mm/sup 2/ containing nine types of test structures was implemented using 0.25 /spl mu/m logic backend of line process. This simple and efficient killer defect identification of process steps is employed as yield enhancement strategy.

Novel assessment of process control monitor in advanced semiconductor manufacturing: a complete set of addressable failure site test structures (AFS-TS)

This work describes the implementation of a novel assessment of process control monitor in advanced semiconductor manufacturing. It manifests the design and simulation results of addressable failure site test structures. Four novel test structures with three level interconnects have been developed and validated with an in-house simulation system. The novel test structures are used to identify the locations of killer defects. A test chip of 22/spl times/6.6 mm/sup 2/ containing four types test structures was implemented using a 0.25 /spl mu/m logic backend of line process. This simple and efficient test structure for killer defect identification demonstrated its superiority in yield enhancement.

Investigation of monotonous increase in saturation-region drain current during hot carrier stress in N-type Lateral Diffused MOSFET with STI

Monotonous increase of saturation drain current Idsat but linear-region drain current Idlin reduction during hot carrier injection (HCI) stress is observed in N-type Lateral Diffused MOSFET. But the phenomenon of Idsat increase is contrary to what we typically observed during HCI stress. The increase of Idsat has been attributed to the increase of saturation substrate current Ibsat after HCI stress. TCAD simulations showed that the lateral electric field increases under the high gate bias when a significant amount of electron trapping occurs along the STI corner in the drift region. The trapped electrons will change the distribution of localized electric potential and will result in the substrate current Ib increase. It is also observed that the 1st Ib peak at lower Vgs degrades, consistent with the reduction of drain and source current, due to HCI induced electron trapping. In another word, the electron trapping has two competing effects - one is with current degradation at lower Vgs and the other is with the electric field enhancement that causes the Idsat to increase at higher Vgs.

Addressable failure site test structures (AFS-TS) for process development and optimization

Two types of addressable failure site test structures are developed. In-house program is coded to extract the electrical information and simulate the failure mode. A complete set of test structure modules for 0.25 um logic backend of line process is implemented in a test chip of 22/spl times/6.6 mm/sup 2/. By using the novel test structure, the yield analysis and defect tracking of BEOL process development as well as low-k Fluorinated SiO/sub 2/ (FSG) process optimization are demonstrated.

Scrubber clean process induced CDM ESD-like: CSM (Charged Surface Model) event caused by dummy patterns

This paper describes a process-induced damage phenomenon on the Poly-Insulator-Poly (PIP) capacitor of mixed-mode circuit during the scrubber clean after Spin-On-Glass (SOG) layer deposition. The damage mechanism is the generated charges during the scrubber clean flow through the SOG film, metal-2 stripe, via hole and to dummy metal-1 stripe, and then charge up the parasitic capacitor (dummy metal-1 stripe / Poly-2). These stored charges can be instantly discharged to the nearby PIP capacitor and burn out the dielectric. The damage symptom is similar to but not the same as CDM ESD event, where the charges are stored in the package and flow from the substrate and through the IO pad to a pin. For this difference, this new phenomenon is named as the CSM (Chare Surface Model) event.

Defect detection for short-loop process and SRAM-cell optimization by using addressable failure site-test structures (AFS-TS)

This work describes the utilization of a novel test structure called addressable failure site test structure for short-loop defect detection and proposed a prototype test structure for SRAM process defect detection in advanced semiconductor manufacturing. The novel test structures are used to identify the locations of killer defects which are then used to wafer map defect sites. This simple and efficient killer defect identification of process steps is employed as yield enhancement strategy.

Mechanism and annihilation of shallow-trench-isolation-enhanced poly-mask-edge N + /P-well junction leakage

The dislocation at the trench corner under Poly mask edges was found to be the major killer of junction leakage in generic logic technology. The impact of the sacrificial oxide (SAC-OX) of the well ion implantation (I/I) module and the source/drain (S/D) I/I to the defect formation are investigated for the first time. The influence on N+/P-Well junction leakage caused by the I/I sacrificial oxide from the Rapid Thermal Oxidation (RTO) and Furnace Oxidation (FO) are evaluated by using the process monitoring test structures. Based on the analysis of test structures and the yield evaluation of product, the optimized condition is proposed.

Optimization of low-k dielectric (fluorinated SiO/sub 2/) process and evaluation of yield impact by using BEOL test structures

This work describes the optimization of low-k dielectric process and evaluation of yield impact by using back end of line (BEOL) test structures. Three splits of the low-k dielectric process were compared with high-density-plasma un-doped-silicon-glass (HDP-USG) process and are electrically characterized with the test structures of the BEOL unit process and integration process parameter extraction. The interconnect capacitance is used as the optimization criteria of low-k dielectric process and the yield impact is reviewed for the concern of manufacturing.