Kelvin Yih-Yuh Doong

Study on STI mechanical stress induced variations on advanced CMOSFETs

Impact of shallow trench isolation (STI) induced mechanical stress on MOSFET drive current is investigated by means of a full-matrix active area layout experiment in advanced CMOS process technology. It turns out remarkably that transistor drive current density per unit width is not independent of the active area size, particularly along the direction of the channel current flow. Opposite sensitivities are observed between n- and p-MOSFETs with respect to lateral active area size. The role of gate placement inside the active area is also addressed. A statistical analysis scheme to find principal components is carried out as well.

Field-Configurable Test Structure Array (FC-TSA): Enabling Design for Monitor, Model, and Manufacturability

This work is designated to provide a common frame work of test chip design for technology development and process routine monitor, called as field-configurable test structure array (FC-TSA), which can accommodate and test the various types of test structures including transistors, diodes, and resistors. To minimize the probe-pad number and fully utilize area to maximize the area design efficiency, the memory addressing design scheme is implemented to select the device-under-test in a test chip. With the aid of using adjustable channel width of transmission gates, the input resistance of FC-TSA cell can be parameterized and configured to match with the parasitic resistance of various test structures, moreover, the background leakage could be minimized to meet with 1nA design specification. Two types of array test structures, 12/spl times/25 and 40/spl times/25, are implemented with generic logic process to demonstrate the design feasibility. The measurements of transistor set and process monitor test structures are reviewed and corresponding models are discussed.

Addressable failure site test structures (AFS-TS) for CMOS processes: Design guidelines, fault simulation, and implementation

As technologies scale down, semiconductor manufacturing processes require more and more areas for test structures to ensure accurate yield estimation. This paper presents design guidelines for test structures with addressable failure sites to efficiently utilize a given area. Different types of test structures with three-level interconnects are developed and validated using a novel simulation system. Based on the proposed algorithm, single and multiple defects can be detected and identified precisely without ambiguity. The methodology standardizes the design of test structures for defect capturing as well as their usage within a common pad frame, which can be shared for various processes and applications. A test chip of 22/spl times/6.6 mm/sup 2/ containing a variety of types of these test structures was implemented to demonstrate the design feasibility.

Design and simulation of addressable failure site test structure for IC process control monitor

A novel test structure to ensure failure addressable and high-density test structure of semiconductor process control monitor with a limited number of contact pads required for electrical test is described. The placement and routing scheme requires only two levels of conductive layers, and provides the maximum number of bridging and continuity test structure units. A graph model is developed to manifest the spatial configuration of test structure units and simplify the complexity of fault detection. Also, a generic algorithm of multi-fault detection was developed.

Novel assessment of process control monitor in advanced semiconductor manufacturing: a complete set of addressable failure site test structures (AFS-TS)

This work describes the implementation of a novel assessment of process control monitor in advanced semiconductor manufacturing. It manifests the design and simulation results of addressable failure site test structures. Four novel test structures with three level interconnects have been developed and validated with an in-house simulation system. The novel test structures are used to identify the locations of killer defects. A test chip of 22/spl times/6.6 mm/sup 2/ containing four types test structures was implemented using a 0.25 /spl mu/m logic backend of line process. This simple and efficient test structure for killer defect identification demonstrated its superiority in yield enhancement.

Electrical characterization of model-based dummy feature insertion in Cu interconnects

A methodology is proposed to characterize the electrical performance of model-based dummy feature insertion in Cu interconnect. Two types of test structures were designed to explore the electrical performance discrepancy between the rule-based and model-based dummy feature insertion. The sheet resistance dependency on design rule is characterized at the various density conditions. 2-D field solver extracts the parasitic capacitance caused by dummy feature insertion. A model-based dummy feature insertion algorithm using randomized shapes is proposed to assist the uniformity control of Cu CMP and MIT/SEMATECH 854 AZ test vehicle is used to demonstrate the feasibility of the proposed algorithm.

Addressable failure site test structures (AFS-TS) for process development and optimization

Two types of addressable failure site test structures are developed. In-house program is coded to extract the electrical information and simulate the failure mode. A complete set of test structure modules for 0.25 um logic backend of line process is implemented in a test chip of 22/spl times/6.6 mm/sup 2/. By using the novel test structure, the yield analysis and defect tracking of BEOL process development as well as low-k Fluorinated SiO/sub 2/ (FSG) process optimization are demonstrated.

4K-cells Resistive and Charge-Base-Capacitive Measurement Test Structure Array (R-CBCM-TSA) for CMOS Logic Process Development, Monitor and Model

To maximize the design efficiency of the test chip area and maintain the high accuracy measurement requirement of resistors and capacitors, a 4K-cells resistive and charge-base capacitive test structure array is designed for CMOS logic process development, monitor and model. The test chip utilizes 4-terminal (one of 4 is strongly grounded) Kelvin force/sense measurement for resistive-type and charge-base capacitance measurement (CBCM) for capacitive-type test structures. With the aid of memory-addressing design scheme, any one of the device-under-test in an array can be randomly or sequentially selected for testing with all of them sharing a common probe pad group. To accelerate the testing speed, the address control signals of 8 test structure array are connected in parallel for synchronized parallel testing. A 32×16×8 test structure array has been implemented by utilizing a state-of-the-art logic process to demonstrate design feasibility. The results confirm the excellence of this architecture in measurement with 0.1fF for capacitive and 0.1 ohm for resistive systematic errors, and 7 times testing speed improvement.

Library-based process test vehicle design framework

This work describes a test vehicle design framework, which minimizes the discrepancy among design rule set, tests structure design and testing plan. The framework is composed of the symbolic design rule set, Parametereized-Device, test structure generator, and test vehicle generator. An approach for simplification and consolidation of test structure is proposed to derive the concise test structure library. Finally, implementation of test vehicle is presented.

Design and integration of electrical-based dimensional process-window checking infrastructure

The purpose of this work is to provide a design infrastructure for electrical-based dimensional process-window checking. With the aid of the novel test vehicle design platform, the discrepancy among design rule set, test structure design and testing plan can be minimized. Using the function-independent Test Structure Design Intellectual Properties (TSD-IP) provided by this infrastructure, the process-window could be quantified as the electrical testing of test structures. A cross-generation (130 nm-90 nm) test vehicle which focuses on the evaluation of overlay and critical dimension variation across the intra- and inter-photo field is enacted to demonstrate the design framework.