Charles Kuznia

Smart-pixel-based network interface chip

We present the design and experimental setup of an optically interconnected smart-pixel network interface chip designed to implement a collisionless multichannel-access control protocol. The design demonstrates the cointegration of optoelectronic pixel modules of various levels of complexity for dense, high-speed interconnection of highly functional digital logic components typical of multiprocessor network routers.

Demonstration and architectural analysis of complementary metal-oxide semiconductor /multiple-quantum-well smart-pixel array cellular logic processors for single-instruction multiple-data parallel-pipeline processing.

We present an optoelectronic-VLSI system that integrates complementary metal-oxide semiconductor/multiple-quantum-well smart pixels for high-throughput computation and signal processing. The system uses 5 x 10 cellular smart-pixel arrays with intrachip electrical mesh interconnections and interchip optical point-to-point interconnections. Each smart pixel is a fine grain microprocessor that executes binary image algebra instructions. There is one dual-rail optical modulator output and one dual-rail optical detector input in each pixel. These optical input-output arrays provide chip-to-chip optical interconnects. Cascading these smart-pixel array chips permits direct transfer of two-dimensional data or images in parallel. We present laboratory demonstrations of the system for digital image edge detection and digital video motion estimation. We also analyze the performance of the system compared with that of conventional single-instruction-multiple-data processors.

TIME MULTIPLEXING AND CONTROL FOR OPTICAL CELLULAR-HYPERCUBE ARRAYS

We discuss the cellular-hypercube optical free-space interconnection architecture and its implementation by two-dimensional smart-pixel optoelectronic cellular arrays. We emphasize the behavior of the cellular hypercube in performing shift-invariant parallel shifts of data, a basic requirement of most single-instruction multiple-data algorithms. We present a time-multiplexing scheme for realizing the cellular hypercube, showing that the communication time is inversely proportional to the number of optical detectors per cell. We also present an improved hybrid interconnection network with improved performance that combines the cellular hypercube and mesh, using optics for the longer-distance connections and electronics for nearest-neighbor connections.

Translucent smart pixel array (TRANSPAR) chips for high throughput networks and SIMD signal processing

We present a novel architecture for an optical network, translucent smart pixel array (TRANSPAR), having smart pixel devices which effectively function in an optically translucent manner. The network protocol is similar to carrier-sense multiple-access/collision-detection (CSMA/CD) commonly used in Ethernet, but adapted to a ring configuration using optical parallel packets in free space. The TRANSPAR devices also function as a fine-grain mesh-connected parallel pipeline array for image and video signal processing. We designed, fabricated, and are currently testing the TRANSPAR smart pixel devices and network node hardware. This paper presents the network architecture, tradeoffs, and design decisions, the testing results to date, and ends with considerations on practicality and future scalability.

Two-dimensional parallel pipeline smart pixel array cellular logic (SPARCL) processors-chip design and system implementation

We describe the chip design and system implementation of an optoelectronic parallel pipeline processing system composed of cascaded stages of smart pixel array cellular logic (SPARCL) processors interconnected with free-space digital optic channels. The SPARCL processing elements are arranged in a two-dimensional array, and each contains an independent optical input/output port and electrical nearest-neighbor local interconnections. The smart pixels are implemented using GaAs-GaAlAs multiple-quantum-well diode arrays flip-chip bonded onto complementary metal-oxide-semiconductor circuitry through the Bell Labs Lucent Technologies/George Mason University optoelectronic VLSI foundry. This system provides efficient execution of single-instruction multiple-data algorithms on large data fields and images.

An asynchronous optical token smart-pixel design based on hybrid CMOS-SEED integration

We describe an asynchronous optical token-based arbitration circuit designed and implemented using hybrid CMOS-SEED smart-pixel technology. Our design exploits fast, global communication chip links offered by free-space optics while providing nontrivial logic functionality required by electronic-based network operations. Thus, we show that smart-pixel technology is applicable to multiprocessor interconnection networks.

Performance-based adaptive power optimization for digital optical interconnects

Optical links are traditionally set to transmit maximum power for worst-case loss and consequently to dissipate more power than is required. We describe a technique to minimize power consumption based on the measured bit-error rate (BER) of the link. This technique uses a novel power-negotiation algorithm that optimizes the link power setting to achieve minimum power dissipation for a target BER. A 0.5 microm complementary metal-oxide semiconductor optical transceiver chip was fabricated, and a free-space optical interconnect system was built for validation. The results showed that the algorithm was able to find the optimum power settings for the VCSELs for a target BER and to account for dynamic changes such as variation in the optical loss in the system.

Modulator and VCSEL-MSM smart pixels for parallel pipeline networking and signal processing

TRANslucent Smart Pixel Array (TRANSPAR) systems perform high performance parallel pipeline networking and signal processing based on optical propagation of 3D data packets. The TRANSPAR smart pixel devices use either self-electro- optic effect GaAs multiple quantum well modulators or CMOS- VCSEL-MSM (CMOS-Vertical Cavity Surface Emitting Laser- Metal-Semiconductor-Metal) technology. The data packets transfer among high throughput photonic network nodes using multiple access/collision detection or token-ring protocols.

Architecture and optical system design for translucent smart pixel array (TRANSPAR) chips

We present the architecture and optical design for a smart pixel optoelectronic system that performs very high throughput networking and three-dimensional single-instruction multiple-data (SIMD) parallel signal processing. The smart pixel chip in the system is called a TRANslucent Smart Pixel Array (TRANSPAR), and it contains a 2-D array of fine-grain processing elements with additional functionality for performing carrier-sense multiple access with collision detection (CSMAJCD) networking. This chip is currently being fabricated by Lucent through the DARPA/GMU/CO-OP foundry program in 0.5 micron CMOS with flip-chip bonded multiple quantum well (MQW) optical modulators and detectors (II.

TRANslucent smart pixel ARray (TRANSPAR) chips for high throughput networks and SIMD signal processing

We present a smart pixel device for networking and parallel processing based on the use two-dimensional arrays optical channels between VLSI chip planes.