Wolfgang Sauter

Chip-to-package interaction for a 90 nm Cu / PECVD low-k technology

A summary of chip-to-package interaction (CPI) evaluations for a 90 nm PECVD low k technology will be discussed. This review will cover a 90 nm technology that uses Cu dual damascene interconnections with a SiCOH (K /spl sim/ 3.0) CVD BEOL insulator stack across multiple wirebond package types and flipchip C4 ceramic and organic packages. It will be shown that with the use of IBMs internally engineered SiCOH BEOL insulator, CPI is not an issue with this technology node.

Problems with wirebonding on probe marks and possible solutions

As density of VLSI devices continues to increase at a rapid rate, extensive efforts are being made in development of fine pitch wirebond for IC packages to utilize higher U0 bonds required for recent fme pitch wirebond applications, the effect of the probe mark under the wirebond ball is counts while shrinking chip sizes. With the small size of ball

Solder Bump Electromigration and CPI Challenges in Low-k Devices

Understanding and managing both chip-to-package interaction (CPI) and solder bump electromigration (EM) is becoming an increasing challenge for flip chip plastic ball grid array (FCPBGA) packaging. Requirements for state-of-the-art device technologies include shrinking of feature dimensions with respect to the prior technology node, faster speed, higher power, increased die size and RoHS compliance. To meet these requirements, device designs typically employ promising new low-k dielectric materials, unique construction elements, copper interconnections and Pb-free solder bumps.

Chip Package Interaction for 65nm CMOS Technology with C4 Interconnections

This paper discusses the chip package interaction (CPI) for a 65 nm low k BEOL CMOS chip assembled to an organic package. Inter-level dielectrics with k~3.0 and k~2.7, with oxide terminations, were used in combination with both Sn/Pb and lead-free C4s. Various underfill compounds were tested to determine their effectiveness in mitigating chip stresses without significantly impairing C4 fatigue life. A summary of the reliability stress results will be presented.

Capacitors on organic modules: a new THB failure mode and method of detection

Multi-terminal low inductance capacitors (MTLICs) are used widely throughout the electronics industry to aid with voltage noise suppression and to manage high speed switching currents. They are implemented on system level cards as well as microprocessors and ASICs. MTLIC component dimensions are getting smaller with increased requirements on capacitance/inductance, driving more Ni plates (up to ∼160), thinner dielectrics and therefore resulting in an increased risk for failure in temperature, humidity and bias stressing. Traditionally, MTLICs have been more robust than the modules they are used on - but this may be changing.

Selective nickel and gold plating for enhanced wire bonding technology

Nickel and gold are electrodeposited on wire bond pads by a newly developed selective plating process in which plating is done without photoresist. The gold terminal metal offers exciting advantage over the traditional aluminum metallurgy. The unique self-encapsulating structure of gold and nickel over copper seed is illustrated. The plating tool, process control and thickness uniformity are described. We have evaluated this structure with probing, aging and stress under high temperature (200degC) in conjunction with bonding. We also varied the bonding conditions to allow a wider choice of inter-level dielectrics and structure/device placement under pads. All the data shows that this is a viable alternative to the current process of record

Manufacturability and reliability of different size wirebonds on different Al pad structures

The manufacturability and reliability of wirebonds depends on many factors, most of which are linked to the BEOL wafer fabrication process. This paper presents a detailed experimental analysis of the effect of pad thickness and liner levels on the quality of the interconnection. Varying ball sizes are evaluated and compared for different target pitch applications. Thermal aging of the wirebonds with subsequent wire pull and ball shear was studied and the challenges of this test are described.

Chip cracks during assembly: Finding and eliminating the critical defect

During the bond and assembly process of an organic module, the backside of the chip will be in tensile stress. Vertical cracking through the Silicon chip (as shown in Figure 1) can occur when the strength of the chip is lower than the stress that is applied through the bond and assembly processes and associated materials.