Eric D. Perfecto

Multilevel thin film packaging: applications and processes for high performance systems

IBM has developed and implemented multilayer thin films (MLTF) for both high end and cost-performance systems since the early 1980s. Copper-polymer and aluminum-polymer multilayer thin films have been implemented on silicon, alumina, and glass-ceramic substrates. The various MLTF implementations are: Two layers of Cu-polyimide interconnection on dry pressed alumina for single and dual chip applications, using wet etch of polyimide and subtractive etching of Cr-Cu-Cr for wiring. One to two layers of planar Cu-polyimide interconnection on alumina and glass-ceramic multichip modules for redistribution of chip I/Os to the ceramic vias, using laser ablation for via definition, subtractive etching of Cr-Cu-Cr for wiring definition, and liftoff for bonding pad definition. Four layers of Al-polyimide multichip interconnection on silicon substrates, using reactive ion etching for via definition, subtractive etching of aluminum for wiring definition, and evaporation through a mask for bonding pad definition. Four to five layers of planar Cu-polyimide interconnection on glass-ceramic substrates, using laser ablation for via definition, photosensitive polyimide (PSPI) lithography and blanket electroplating for wiring definition, and liftoff for bonding pad definition. Four or five layers of non-planar Cu-polyimide interconnection on alumina, silicon, and glass-ceramic substrates, using laser ablation or photosensitive polyimide lithography for via definition, additive electroplating or subtractive etching of Cu for wiring definition, and additive electroplating for bonding pad definition. In this paper we discuss the evolution of these thin film technologies as well as the process choices, their merits, and the reasoning behind the various choices. >

Measurement of dielectric anisotropy of BPDA-PDA polyimide in multilayer thin-film packages

The measured dielectric anisotropy of BPDA-PDA polyimide, obtained from a specially designed test vehicle, is presented. The multilayer thin-film structure is representative of its actual use in multichip carrier (MCM-D) applications both from the cross sectional dimensions and fabrication sequence point of view. Modeling is performed using finite-element and electromagnetic techniques and the effect of anisotropy on signal propagation and crosstalk are verified through time-domain measurements. >

C4NP technology: Manufacturability, yields and reliability

As a part of IBM movement from Pb-rich solders to Pb-free solder, a new low cost process has been developed to deposit the solder to a capture, or under bump metal (UBM) pad, with Suss MicroTech Inc as the equipment partner. The controlled collapsed chip connection new process (C4NP) has moved, over the last 2 years, from development into manufacturing for 300 mm wafers. During this transition, a great number of process improvements have resulted in high fabrication yields. Manufacturing robustness has been achieved by clearly identifying the processes which affect the C4 structural integrity. The solder composition has been optimized to improve its mechanical properties as well as low alpha emission rate requirement. Sector partitioning methodology was used to obtain root cause for various defects which then, through replication studies, were confirmed. Key process improvements in the capture pad build, mold fabrication, and mold fill tool have been accomplished as the process has matured. Thermal undercut was identified as a mechanism of Cu seed consumption when no top Cu was available on top of the Ni UBM. C4NP technology can produce yields comparable to that of electroplated C4 Bumps. Yield learning model shows a 15% defect reduction per month since the start of the C4NP program. Technology qualification for 300 mm wafers with 200um and 150 um pitch Pb-free C4 bumps has been successfully completed.

Thin-film multichip module packages for high-end IBM servers

A new generation of multilevel thin-film packages has been developed for IBM high-end S/390® and AS/400® systems. Thin-film structures in these packages are nonplanar and can be fabricated by either pattern electroplating or subtractive etching. Selection criteria for choice of fabrication methods are discussed in terms of electrical performance requirements, ground rules, manufacturability, and cost issues. Two problems encountered in the development phase of the nonplanar thin-film structures were 1) accelerated etching of plated Cu features during Cu seed etching, and 2) corrosion of the bottom-surface metallurgy during etching of Cr at the top surface. Effective solutions were developed on the basis of underlying electrochemical phenomena. Finally, reliability stress procedures used to qualify these packages and results of these procedures are presented.

Large format fabrication-a practical approach to low cost MCM-D

The IBM Microelectronics Division at East Fishkill has recently demonstrated the fabrication of thin films for MCM-D on large area panels, 300 mm/spl times/300 mm in size. Fabrication of the thin films was accomplished on IBMs 300 mm development line using immersion development of photosensitive polyimide for via formation and electrolytic plating to define wiring and terminal metal levels. One plane pair of thin films was constructed on Corning glass 7059 panels for 35 /spl mu/m lines on 85 /spl mu/m pitch. In addition, two metal-dielectric levels with 13 /spl mu/m lines on 25 /spl mu/m pitch have also been demonstrated. The 25 /spl mu/m pitch represents the most aggressive groundrule practised in electronic packaging today. The successful production of electrically good substrates at a high yield from a 300 mm panel provides a gateway to significant cost reductions of future MCM-D products. This paper discusses the processes and equipment used to fabricate two different test vehicles, as well as some of the cost and yield considerations associated with large area panel processing for MCM-D packages. >

Wafer IMS (Injection molded solder) — A new fine pitch solder bumping technology on wafers with solder alloy composition flexibility

In this paper, we will describe a new low cost solder bumping technology for use on wafers. The wafer IMS (injection molded solder) process can form fine pitch solder bumps on wafers, while offering greater solder alloy flexibility. This method is also applicable to form uniform solder bump heights when a wafer has different size and shape of I/O pads. The wafer IMS bumping process uses a solder injection head that melts the desired bulk solder alloy composition and then dispenses the molten solder into resist material cavities on wafers within a nitrogen environment. The injected molten solder contacts and wets to the metal pads without flux, thus forming intermetallic compounds at the solder/pad interface. After stripping the resist material, solder bumps exhibit straight side walls and round tops as the solders have solidified inside the cavities of this resist film. This particular geometry is unique and offers a ready-for-substrate bonding condition without an additional reflow step. In the case of using Cu pillars, one resist material is used for both Cu electroplating and molten solder injection. After patterning the resist material, the Cu pillars are electroplated to the desired height, and the remaining cavities of resist material are filled by the injection of molten solder. The final bump height is defined by the thickness of the resist material. Therefore, any non-uniformity of Cu pillar height across a wafer is masked by the final solder bump uniformity. A prototype tool for wafer IMS bumping technology has been developed and solder bumping has successfully been demonstrated with Sn-3.0Ag-0.5Cu solder on 200mm wafers. The test wafer employed interconnects pads of four different diameters and three different shapes. Other solder compositions have also been tried successfully.

A high density, high performance MCM-D/C package: a design, electrical, and process perspective

This paper describes a state-of-the-art seven chip MCM-D/C package currently under production for use as a processor module for the high end of IBMs AS/400 Advanced Series with PowerPC technology. Physical design, process, and electrical design (characterization) is described, and trade-offs made between them are discussed.

Wafer level underfill for area array Cu pillar flip chip packaging of ultra low-k chips on organic substrates

Wafer level underfill (WLUF), coated and B-staged on the wafer before dicing and flip chip bonding, protects and preserves interconnects and Back-End-of-Line (BEOL) structures by the presence of the underfill during the chip joining process. However, there are significant new challenges in formulating WLUF materials and developing the processes for area array flip chip packaging of silicon chips on organic substrates. The use of highly filled WLUF in conjunction with Ultra Low-k (ULK) chips which are larger than 10 × 10 mm and interconnected with Cu pillars to organic substrates has not yet been reported in the literature. It has been very challenging to achieve 100% electrically and metallurgically good Pb-free solder joints without WLUF voids. In this paper, details of flip chip packaging processes with highly filled WLUF materials (60 wt% fillers) will be presented including coating, dicing, bonding, and curing. The size of the test chip was 13×17mm and the test substrate was 42.5×42.5mm with over 8,000 area array interconnects. The chip bumps were 40 micron tall Cu pillars capped with 10 microns of SnAg solder (Ag >; 1.5 wt%) and the pre-solder on the substrate was SnAgCu (Ag >; 3.0 wt%). During the WLUF spin coating process, it is important to maintain uniform filler distribution as well as thickness uniformity. We achieved a tack-free surface after B-stage cure and the surface roughness was less than 0.2 micron. Since the wafer has ULK (k<;2.4) dielectric, the wafer requires laser grooving before the blade dicing to reduce the stress during wafer sawing. We introduced a new dicing method to apply laser grooving for WLUF flip chip packages. When WLUF is used for flip chip packaging of 13×17 mm size chips on organic substrates, the WLUF should be inherently fluxing to achieve metallurgically good solder joints by melting and solidification of the solder during the bonding process because larger size area array chip packages require higher reliability criteria than smaller size peripheral chip packages. However, the flux capability is a likely source of voids in the WLUF after bonding. These voids were eliminated during a post cure process of the WLUF material by using hydrostatic pressure. In addition, fillers in the 60 wt% loaded WLUF must not be trapped in the solder joints, so the viscosity of the WLUF must remain low until the solder fully melts to make metallurgically good interconnections from the center to the corners of the chip. Cross sectional analysis was used to study the geometry of flip chip joints and filler distribution in the perimeter and the center of the chip. It was confirmed that solder joints were metallurgically good with no filler entrapment and that the filler was uniformly distributed. Non destructive X-ray images showed that there was no solder joint bridging in the entire chip area. C-SAM (C-Mode Scanning Acoustic Microscopy) confirmed that the integrity of the BEOL layer was preserved and that any WLUF voids that existed after bonding had been eliminated after full cure under hydrostatic pressure.

C4NP as a High-Volume Manufacturing Method for Fine-Pitch and Lead-Free FlipChip Solder Bumping

More and more high-end microelectronic devices are being packaged by using solder bumps as the method of interconnection. The two main technologies are flipchip in package (FCiP) and wafer level chip scale package (WLCSP). The main difference is that FCiP devices are placed on a substrate which then interconnects to the PC board (PCB). WLCSP devices connect directly onto the board. There are various solder bumping technologies used in volume production. These include electroplating, solder paste printing, evaporation and the direct attach of preformed solder spheres. FCiP demands many small bumps on tight pitch whereas WLCSP typically requires much larger solder bumps. All these established technologies have important limitations for fine pitch bumping especially when it comes to lead-free solder alloys. The most commonly used method of generating fine-pitch solder bumps is by electroplating the solder. This process is difficult to control and costly, especially when it comes to lead-free solder alloys. These challenges in the transition to lead-free solder bumping has led the European Union to grant exemptions from the ban of lead in certain solder bumping applications. However, the pressure to move to lead-free continues for the entire industry. C4NP (C4-new process) is a new solder bumping technology developed by IBM and commercialized by Suss MicroTec. C4NP addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. C4NP is a solder transfer technology where molten solder is injected into pre-fabricated and reusable glass templates (molds). Mold and wafer are brought into close proximity and solder bumps are transferred onto the entire 300mm (or smaller) wafer in a single process step. C4NP technology is capable of fine pitch bumping while offering the same alloy selection flexibility as solder paste printing. The simplicity of the C4NP process makes it a low cost solution for both, fine-pitch FC in package as well as WLCSP bumping applications. This paper provides a summary of manufacturing and reliability results of C4NP bumped high-end logic devices and how they compare to electroplated lead-free solder bumps. It discusses the relevant process equipment technology and the novel requirements to run a HVM (high volume manufacturing) C4NP process. The paper also talks about the C4NP manufacturing cost model and elaborates on the cost comparison to alternative bumping techniques. The data in this paper is provided by IBMs packaging operation at the Hudson Valley Research Park in East Fishkill, NY

Differential heating/cooling chip joining method to prevent chip package interaction issue in large die with ultra low-k technology

A differential heating/cooling chip join method was developed for Pb-free flip chip packaging of ultra low-k (ULK) technology Si chips on organic substrates to prevent Chip-Package Interaction (CPI) - related damage upon chip joining. A chip was mounted to a bonder head and a substrate was located on a base plate and they were held at different elevated temperatures during the bonding process. The temperature difference between the Si chip and the organic substrate during assembly provides a substantially matched thermal expansion and minimizes stress induced by coefficient of thermal expansion (CTE) mismatch. From the modeling study, it was confirmed that chip warpage, Controlled Collapse Chip Connection (C4) stresses/strains, and ULK stresses decreased significantly by differential heating/cooling chip join method, with further improvement noted as the substrate temperature was decreased during the bonding process. X-ray, scanning electron microscope (SEM) and C-mode scanning acoustic microscope (C-SAM) were used to examine the defects after flip chip assembly. Noncontact white light reflectometry was also used to measure the warpage shape of the assembled silicon chip and the organic substrate. Observation under C-SAM indicated that fractures in the ULK layers were dramatically reduced by the differential heating/cooling chip joining process compared to the conventional reflow process. Non-destructive X-ray images indicated there were no solder bridging in any area of the chip interconnects. The experimental results showed that the differential heating/cooling chip join process can effectively reduce fractures in the ULK layers and prevent C4 bump bridging in a large die package with low-K dielectric constant device integration and high Ag content solder bumps.