Christopher D. Muzzy

Chip-to-package interaction for a 90 nm Cu / PECVD low-k technology

A summary of chip-to-package interaction (CPI) evaluations for a 90 nm PECVD low k technology will be discussed. This review will cover a 90 nm technology that uses Cu dual damascene interconnections with a SiCOH (K /spl sim/ 3.0) CVD BEOL insulator stack across multiple wirebond package types and flipchip C4 ceramic and organic packages. It will be shown that with the use of IBMs internally engineered SiCOH BEOL insulator, CPI is not an issue with this technology node.

Influence of underlying interlevel dielectric films on extrusion formation in aluminum interconnects

Knowledge of the mechanical properties of interlevel dielectric films and their impact on submicron interconnect reliability is becoming more and more important as critical dimensions in ultralarge scale integrated circuits are scaled down. For example, lateral aluminum (Al) extrusions into spaces between metal lines, which become more of a concern as the pitches shrink, appear to depend partially on properties of SiO2 underlayers. In this article nanoindentation, wafer curvature, and infrared absorbance techniques have been used to study the mechanical properties of several common interlevel dielectric SiO2 films such as undoped silica glass using a silane (SiH4) precursor, undoped silica glass using a tetraethylorthosilicate precursor, phosphosilicate glass deposited by plasma-enhanced chemical vapor deposition and borophosphosilicate glass (BPSG) deposited by subatmosphere chemical vapor deposition. The elastic modulus E and hardness H of the as-deposited and densified SiO2 layers are measured by nanoi...

Chip Package Interaction for 65nm CMOS Technology with C4 Interconnections

This paper discusses the chip package interaction (CPI) for a 65 nm low k BEOL CMOS chip assembled to an organic package. Inter-level dielectrics with k~3.0 and k~2.7, with oxide terminations, were used in combination with both Sn/Pb and lead-free C4s. Various underfill compounds were tested to determine their effectiveness in mitigating chip stresses without significantly impairing C4 fatigue life. A summary of the reliability stress results will be presented.

Chip package interaction evaluation for a high performance 65nm and 45nm CMOS Technology in a stacked die package with C4 and wirebond interconnections

An evaluation of 65 nm and 45 nm CMOS technology in a stacked die package is presented. The technology uses SiCOH advanced low K and ultra low K back end of line (BEOL) for high performance. A BEOL specific test vehicle was fabricated in these technologies and both flip chip and wirebond die used in a stacked die configuration. Manufacturability evaluations for bond and assembly processes and materials were performed and reliability studies completed on assembled modules. Results will show that the technologies are reliable in this packaging configuration.

The Mechanical Properties of Common Interlevel Dielectric Films and Their Influences on Aluminum Interconnect Extrusions

Knowledge of the mechanical properties of interlevel dielectric films and their impact on sub-micron interconnect reliability is becoming more and more important as critical dimensions in ULSI circuits are scaled down. For example, lateral aluminum (Al) extrusions into spaces between metal lines, which become a more of a concern as the pitches shrink, appear to depend partially on properties of SiO 2 underlayers. In this paper, the mechanical properties of several common interlevel dielectric SiO 2 films such as undoped silica glass using a silane (SiH 4 ) precursor, undoped silica glass using a tetraethylorthosilicate (TEOS) precursor, phosphosilicate glass (PSG) deposited by plasma-enhanced chemical vapor deposition (PECVD) and borophosphosilicate glass (BPSG) deposited by sub-atmosphere chemical vapor deposition (SACVD) were studied. Among the four common interlevel layers, BPSG exhibits the smallest modulus (E), hardness (H) and the highest the coefficients of thermal expansion (CTE). BPSG again has the lowest as-deposited compressive stress and the lowest local Si-O-Si strain before annealing. Stress interactions between the various SiO 2 underlayers and the Al metal film are further investigated. The impact of dielectric elastic properties on interconnect reliability during thermal cycles is proposed.