Charles W. Koburger

Integration of chemical-mechanical polishing into CMOS integrated circuit manufacturing

Abstract Planarization by chemical-mechanical polishing (CMP) has been exploited by IBM in the development and manufacture of CMOS products since 1985. Among the products that use this technology are the 4-Mbit DRAM (which uses polysilicon, oxide, tungsten-line and tungsten-stud planarization) and its logic family (which uses four oxide and four tungsten-stud planarization steps). CMP is also used in the planarization of oxide shallow isolation trenches, as in the 16-Mbit DRAM. Reduced sensitivity to many types of defects is possible with CMP. A wafer that is truly flat is easier to clean, eliminates step coverage concerns, provides for better photolithographic and dry etch yields, and generally minimizes complications from prior level structures. Oxide CMP reduces sensitivity to certain pre-existing defects, such as crystalline inclusions or foreign material in an interlevel dielectric. Metal CMP can reduce the incidence of intralevel shorts relative to conventional RIE processing. Random defects associated with CMP, such as slurry residues and mechanical damage, are controlled by careful optimization of the post-polish clean and of the polish process itself. Systematic defects, such as incomplete planarization over very large structures, are controlled by process optimization and prudent design limitations. These include such things as constraints on the image size, the distance between images, and/or the local pattern density. Since its introduction in the 4-Mbit DRAM, there has been a steady increase in the use of chemical-mechanical polishing in IBM CMOS products. The number of steps, processes and materials polished continue to rise, both in current and planned future products. Individual applications range from the simple removal of back-side films to complex insulator or metal planarization requiring high removal uniformity. The process tolerances delivered by CMP have decreased faster than image size, even in the face of dramatic increases in circuit and layout complexity. CMP tools are installed in IBM semiconductor manufacturing and development sites worldwide. Chemical-mechanical polish processes and applications provide unique leverage to IBM products, and are a crucial part of both current and planned IBM CMOS technologies.

Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond

We present UTBB devices with a gate length (L<inf>G</inf>) of 25nm and competitive drive currents. The process flow features conventional gate-first high-k/metal and raised source/drains (RSD). Back bias (V<inf>bb</inf>) enables V<inf>t</inf> modulation of more than 125mV with a V<inf>bb</inf> of 0.9V and BOX thickness of 12nm. This demonstrates the importance and viability of the UTBB structure for multi-V<inf>t</inf> and power management applications. We explore the impact of GP, BOX thickness and V<inf>bb</inf> on local V<inf>t</inf> variability for the first time. Excellent A<inf>Vt</inf> of 1.27 mV·µm is achieved. We also present simulations results that suggest UTBB has improved scalability, reduced gate leakage (I<inf>g</inf>) and lower external resistance (R<inf>ext</inf>), thanks to a thicker inversion gate dielectric (T<inf>inv</inf>) and body (T<inf>si</inf>) thickness.

Oxidation-induced defect generation in advanced DRAM structures

Structures containing deep-trenched storage capacitors and shallow-trench isolation were examined in patterns suitable for future generation dynamic RAMs (DRAMs). These same effects were also examined in similar structures which included only the shallow isolation trenches. Observed was a strong interaction between the deep and shallow trenches, which makes structures which incorporate both types much more susceptible to oxidation-induced defect generation than those without deep trenches. It was observed that at higher oxidation temperatures, more oxide can be grown before defects are generated. This is interpreted as a combination of more-efficient visco-elastic relaxation in the oxide and a lower differential oxidation rate between the

Simple, fast, 2.5-V CMOS logic with 0.25-/spl mu/m channel lengths and damascene interconnect

An advanced half-micron CMOS technology is demonstrated. Devices with 0.25-/spl mu/m channel lengths provide high speed. Reduced supply voltage is employed to provide reliability with low-cost processing. A damascene tungsten interconnect fabricated using a nitride etch stop allows use of 30-/spl mu/m/sup 2/ SRAM cells.<<ETX>>

Copper contact metallization for 22 nm and beyond

We used Cu contact metallization to solve one of the critical challenges for 22 nm node technology. Cu contact metallization allowed us to demonstrate worlds smallest and fully functional 22 nm node 6T-SRAM [1]. Cu contact metallization was executed using CVD Ru-containing liner. We obtained early reliability data by thermally stressing bulk device. Bulk device parameters such as junction and gate leakage currents and overlap capacitance were stable after BEOL anneal stress. We also demonstrated the extendibility of Cu contact metallization using 15 nm contacts.

Robust and low cost copper contact application for low power device at 32 nm-Node and beyond

We have demonstrated the complete copper filling of contact structures at 32 nm- and 22 nm-node dimensions with the conventional PVD only Ta(N)/Cu barrier/seed process. Copper seed process was optimized to obtain the sufficient coverage of copper along the contact hole with the sufficiently wide gap opening at the top by the use of the directional sputtering and the re-sputtering techniques. In addition, this process was implemented on fully integrated 32 nm-node device wafers and the optimized process produced sufficient performance to meet 32 nm-node requirements. The investigation also included two cases with intentional departure from the optimal conditions, one with a low thickness barrier and the other without copper re-sputtering. In both cases negative influence on front-end-of-the-line (FEOL) parameters was observed.

IIB-2 process-dependent properties of three-dimensional capacitors

Capacitance per unit of cell area in silicon MOS IC technologies can be increased by etching convolutions into the semiconductor surface beneath the electrode [1]-[4]. These convolutions are typically formed via directional dry processing (reactive ion etching (RIE)). Energetic plasma process steps, however, have been reported to result in degradation of capacitor MOS properties in both planar [5]-[9] and three-dimensional [3], [4], [10] devices. In our experiments, planar devices formed on etched surfaces display MOS behavior that is normal in all respects when standard pre-oxidation cleaning is performed. Three-dimensional devices, however, can suffer a non-trivial degradation of dielectric breakdown voltage. The degradation is found to result from field enhancement accompanying identifiable topographical features, and is not an inherent result of RIE processing. RIE and post-RIE processing parameters influence the degree of degradation. TEM examination of three-dimensional devices is employed to characterize the physical nature of RIE-fabricated devices, and the observations are correlated with electrical behavior.