Jack A. Mandelman

Challenges and future directions for the scaling of dynamic random-access memory (DRAM)

Significant challenges face DRAM scaling toward and beyond the 0.10-µm generation. Scaling techniques used in earlier generations for the array-access transistor and the storage capacitor are encountering limitations which necessitate major innovation in electrical operating mode, structure, and processing. Although a variety of options exist for advancing the technology, such as low-voltage operation, vertical MOSFETs, and novel capacitor structures, uncertainties exist about which way to proceed. This paper discusses the interrelationships among the DRAM scaling requirements and their possible solutions. The emphasis is on trench-capacitor DRAM technology.

Numerical modeling of advanced semiconductor devices

Numerical modeling of the electrical behavior of semiconductor devices is playing an increasingly important role in their development. Examples that pertain to advanced MOSFETs and bipolar transistors are presented to illustrate the importance of taking into account three-dimensional as well as nonequilibrium and nonlocal physical phenomena to effectively characterize the electrical behavior of such devices.

Complementary visualization and sonification of multidimensional data

Interpretation of multi-dimensional complex data usually involves extracting the relationship between several variables. This is typically done with an interactive visual system . Iugh resolution volumetric data imaging, color, animation, and multiple views are effective tools for data interpretation. Sound can provide an additional and complementary perceptual channel. This presentation focuses on the use of sound with a multi-dimensional imaging system to facilitate the interactive interpretation of complex data. Our methods and system are presented with data from a simulation which computes electron density, hole density, and potential throughout the volume of a three-dimensional semiconductor. The spatial changes and relationships of the three scalar fields are the object of study. Normally the field relations would he examined through multiple visualizations. here, sound is used to augment the visualization by permitting a user to visually concentrate on one field, while listening to the other. Two of the three scalar fields from the simulation arc selected for interpretation and visualized. The 3-dimensional vector gradient of one of them is sonified at a selected focal point within the semiconductor solid. As the current focus i interactively moved through the solid, the representative sound is altered accordingly. The sonification is composed such that local minima and maxima of one of the fields can he found without looking at it.

Array pass transistor design in trench cell for Gbit DRAM and beyond

Aggressive scaling of the DRAM cell size requires minimum dimensions in both the channel length and the channel width of the array pass transistor. As a result of the stringent leakage current requirement, the design for the array MOSFET becomes increasingly challenging as cell size is reduced. In this paper, we present data that illustrate the importance of the channel and the source/drain engineering, along with considerations of minimizing the junction leakage. By utilizing a 512 k array diagnostic monitor, a methodology is presented for optimum array cell design in a statistically reliable manner. Design issues unique to the trench capacitor cell are covered. Alternative biasing schemes that boost the process window are also discussed.

Angled implant fully overlapped LDD (AI-FOLD) NFETs for performance and reliability

Fully overlapped lightly doped drain FOLD n-channel MOSFETs built for the purpose of improving the tradeoff between performance and reliability are discussed. Full gate overlap was achieved by using angled implants to extend LDD (lightly-doped drain) regions beneath the gate edge of devices. The dose and energy of the angled implants were varied. The parasitic overlap capacitance and series resistance as well as the reliability enhancement introduced by the FOLD structure are investigated in detail. The series resistance is shown to be strongly dependent on gate voltage, while the overlap capacitance is found to be reduced significantly by depletion of the FOLD drain regions. The corresponding reduction in hot-carrier-limited channel length more than compensates for the increase in parasitics, indicating substantial enhancement in net drive performance. >

Gate prespacers for high density DRAMs

The channel length of the DRAM transfer gate device continues to shrink aggressively. Conventional scaling techniques are limited in their applicability for the low leakage DRAM transfer device. There is thus a need for novel integration schemes that allow the continued cell shrinkage with only limited shrinking of the channel length. In this paper, we present an integration scheme which allows for a larger gate polysilicon length for a given pitch thus improving array device leakage (by about one generation) for a given technology.

Super-halo asymmetric vertical pass transistor design for ultra-dense DRAM technologies

Device design of the super-halo asymmetric vertical pass transistor embedded in a cost-efficient, litho-friendly 8F/sup 2/ DRAM cell is described. This device not only retains the double-gate feature that provides twice the drive current, but also improves write-back performance critical for DRAM applications while meeting the stringent 1 fA off-current requirement. The key to achieving this degree of optimization is a super-halo angled Vt implant that produces multi-dimensionally graded well doping. The lateral grading provides small body effect and superior write-back performance that facilitates scaling with low wordline swings. The vertical grading leads to reduced short channel effect and de-coupled channel and node doping that not only reduces junction leakage but also allows aggressive scaling of the vertical device channel length.

Array transistor design challenges in trench capacitor DRAM technology

BuriEd Strap Trench (BEST) array cell design has been extended for more than 4 generations. However, significant scaling challenges in planar trench DRAM technology will be encountered below the 0.1 /spl mu/m generation. In this paper, we review the key factors that limit the scaling of the BEST array cell, further analyze the scaling challenges considering design for manufacturability, and finally discuss other design and/or technology innovations including the vertical array transistor to overcome scaling limitations.

Body-doping considerations for high performance 0.1- mu m SOI MOSFETs

Various factors for determining body doping for a high performance 0.1- mu m SOI (silicon-on-insulator) MOSFET technology are considered. Long channel constraints on body doping and thickness for assuring full depletion are treated first. Then short channel considerations for body doping for a high performance 0.1- mu m SOI MOSFET technology are summarized.<<ETX>>

Visualization tool for the scientist/engineer

Continuing advances in supercomputer technology give the scientist/engineer the ability to run increasingly complex computational experiments and simulations. Gaining insight from the flood of simulation resuits is a difficult task for the scientist. This paper presents the Visual interpretation System (VIS), an easy to use, interactive, discipline-independent tool for understanding multidimensional data sets. Components of the VIS are a database manager, a user interface, and a visualization manager. The database manager facilitates discipline-independent visualization and lets the scientist manipulate data with familiar names and attributes. The visualization manager uses an optical model to generate 3D images with a variety of options including opaque and transparent structures, cutouts, and region highlighting. The effectiveness ofthe VIS is demonstrated using data from a 3D simulation of a transistor device.