Mark C. Hakey

Single-Event Upsets and Multiple-Bit Upsets on a 45 nm SOI SRAM

Experimental results are presented on single-bit-upsets (SBU) and multiple-bit-upsets (MBU) on a 45 nm SOI SRAM. The accelerated testing results show the SBU-per-bit cross section is relatively constant with technology scaling but the MBU cross section is increasing. The MBU data show the importance of acquiring and analyzing the data with respect to the location of the multiple-bit upsets since the relative location of the cells is important in determining which MBU upsets can be corrected with error correcting code (ECC) circuits. For the SOI SRAMs, a large MBU orientation effect is observed with most of the MBU events occurring along the same SRAM bit-line; allowing ECC circuits to correct most of these MBU events.

Low Energy Proton Single-Event-Upset Test Results on 65 nm SOI SRAM

Experimental results are presented on proton induced single-event-upsets (SEU) on a 65 nm silicon-on-insulator (SOI) SRAM. The low energy proton SEU results are very different for the 65 nm SRAM as compared with SRAMs fabricated in previous technology generations. Specifically, no upset threshold is observed as the proton energy is decreased down to 1 MeV; and a sharp rise in the upset cross-section is observed below 1 MeV. The increase below 1 MeV is attributed to upsets caused by direct ionization from the low energy protons. The implications of the low energy proton upsets are discussed for space applications of 65 nm SRAMs; and the implications for radiation assurance testing are also discussed.

A high performance 16-Mb DRAM technology

A high performance 16-Mb DRAM technology is presented. The key issues that must be considered to achieve high yield and reduced cost are described. Technology elements include: deep trench capacitor node with thick oxide collar for improved packing density, variable-size shallow trench isolation (STI) for device performance and ease of integration, polysilicon surface strap to connect the capacitor node to the transfer device, and smoothed dep/etched phosphosilicate glass (PSG) passivation. The application of the above technology elements in conjunction with the MINT cell structure makes it possible to achieve a DRAM cell size of 4.13 μm2, using six 0.5-μm critical-dimension and 0.2-μm overlay lithography levels. Up to ten sequential process steps are performed in a single cluster. A 50-ns access time has been demonstrated

Manufacturing with DUV lithography

Deep-UV (DUV) lithography has been developed to scale minimum feature sizes of devices on semiconductor chips to sub-half-micron dimensions. This paper reviews early manufacturing experiences at the IBM Microelectronics Division with deep ultraviolet (DUV) lithography at a 248-nm wavelength. Critical steps in the processing of 1Mb DRAM, 16Mb DRAM, and logic gate conductors in devices are discussed. The evolution of DUV lithography tools is also briefly reviewed.

Edge lithography as a means of extending the limits of optical and nonoptical lithographic resolution

Lithographic scaling entails continuously increasing resolution while at the same time improving the tolerance control on the printed images. Typically, this has been done by using shorter actinic wavelengths, increasing numerical aperture, compensating reticle patterns and similar methods that serve to enhance the fidelity of the aerial image. In some case, this scaling has been achieved by altering the method of image formation, such as with the use of alternating phase shift reticles, in which the width of the aerial image is established by phase interference rather than of a diffraction-limited process of passing light through a dark masking pattern. This paper describes development of a resist material that provides a new way to scale lithographic patterns, one similar to alternating phase shift lithography in the sense that it prints the edge of an aerial image rather than the entire image as a single pattern. Because the edge of the aerial image is of higher resolution, with smaller components of tolerance than the entire image, this type of resist may provide a new method of scaling.

Heavy Ion Testing With Iron at 1 GeV/amu

A 1 GeV/amu 56Fe ion beam allows for true 90° tilt irradiations of various microelectronic components and reveals relevant upset trends at the GCR flux energy peak. Three SRAMs and an SRAM-based FPGA evaluated at the NASA Space Radiation Effects Laboratory demonstrate that a 90° tilt irradiation yields a unique device response. These tilt angle effects need to be screened for, and if found, pursued with radiation transport simulations to quantify their impact on event rate calculations.

Heavy ion testing at the galactic cosmic ray energy peak

A 1 GeV/u 56Fe ion beam allows for true 90° tilt irradiations of various microelectronic components and reveals relevant upset trends for an abundant element at the GCR flux energy peak.

Cost/benefit analysis of mix-and-match lithography for production of half-micron devices

This paper describes a high-leverage cost-reduction methodology -- advanced mix-and-match lithography. Quantifying the areas of cost savings and cost of ownership is essential in determining the optimum mix-and-match approach. Cost of ownership, using operating data coupled with quantitative models, is analyzed for a half-micron 200 mm fabrication line producing 16 Mbit DRAMs. Utilizing advanced lithography clusters to process the critical levels and cost-effective high-productivity cluster systems for the non-critical levels has resulted in a net production cost savings in excess of 30%. Data comparisons are made between process enhancements and tool types. Areas of cost savings are identified individually and ranked. Further, tradeoffs in learning, cycle time, and technology extendibility are also considered. The cost/benefit analysis demonstrates that mix-and-match lithography is a highly effective method for reducing lithography costs. This paper also discusses the increasing importance of cost modeling to improve competitiveness.

Manufacturing implementation of deep-UV lithography for 500-nm devices

Lithographers have steadily reduced exposure wavelength and increased numerical aperture (NA) to maintain process window and simplicity. The G-line systems of the 1970s gave way to the I-line systems of the late 80s, and then to the deep ultraviolet (DUV) systems of today. This paper describes our characterization of a DUV lithography system for the manufacture of 16-Mb DRAM chips at 500-nm ground rules. The process consists of a positive-tone, aqueous-base developable photoresist with an overcoat for sensitivity control, and an anti- reflective coating (ARC) on selected levels. The exposure tools used are step-and-scan systems with a 0.36 NA and expose bandpass of 240 - 255 nm. Apply and develop processes are clustered with the expose tool to minimize defects, reduce cycle time, and eliminate process variables.