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Dive into the research topics where Che-Chia Wei is active.

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Featured researches published by Che-Chia Wei.


Applied Physics Letters | 1993

Reactively sputtered titanium nitride films for submicron contact barrier metallization

Girish Anant Dixit; Che-Chia Wei; Fu-Tai Liou; Huacheng Zhang

Titanium nitride (TiN) is widely used as a barrier metal for submicron metallization because of its superior thermal stability. Various methods of forming TiN films have been explored. Oxygen passivation of the grain boundaries of the TiN and stoichiometry of the TiN are reported to be the dominant factors in achieving good barrier properties. We report on the structure property correlation of the TiN barrier metal films.Titanium nitride (TiN) is widely used as a barrier metal for submicron metallization because of its superior thermal stability. Various methods of forming TiN films have been explored. Oxygen passivation of the grain boundaries of the TiN and stoichiometry of the TiN are reported to be the dominant factors in achieving good barrier properties. We report on the structure property correlation of the TiN barrier metal films.


international electron devices meeting | 1990

Planarized aluminum metallization for sub-0.5 mu m CMOS technology

Fusen Chen; Yih-Shung Lin; Girish Anant Dixit; R. Sundaresan; Che-Chia Wei; Fu-Tai Liou

The authors describe an aluminum sputter process, called the Al-plug process, which results in complete filling of submicron contacts and vias of various sizes. The process can be done in a conventional sputtering system. Material and electrical characterization of the film and the implementation of this process in submicron integrated circuits are presented.<<ETX>>


Applied Physics Letters | 1992

Transmission electron microscopy characterization of defects resulting from the polycrystalline silicon buffered local oxidation of silicon isolation process

Girish Anant Dixit; Robert Louis Hodges; J. W. Staman; Frank Randolph Bryant; R. Sundaresan; Che-Chia Wei; Fu-Tai Liou

Polybuffered LOCOS is used for isolation of active devices in submicron integrated circuits. Many papers have reported on the defects resulting from this process. We report, for the first time, on the structure and composition of these defects and relate the defects to a phenomenon similar to the traditional Kooi effect [E. Kooi, J. G. van Lierop, and J. A. Apples, J. Electrochem. Soc. 123, 1117 (1976)].


MRS Proceedings | 1992

Advanced Planarized Aluminum Metallization Process

Fusen Chen; G. A. Durit; J. W. Staman; Che-Chia Wei; Fu-Tai Liou

Sputtered aluminum has been used for interconnection in integrated circuits because of its low resistivity. However conventional sputtered aluminum has two important drawbacks, poor step coverage and poor planarization, which make it unsuitable for eubmicron multi-level interconnect process. CVD tungsten is an attractive option for forming plugs and interconnects but suffers several drawbacks. It is therefore preferable to use aluminum for both plugs and interconnections due to its simplicity and established prior history. We have developed a fully planarieed aluminum metallization process which produces void free contact plugs. In order to verify the filling of the contact plugs, we have carried out extensive SEM analysis using secondary electron and backscattered electron imaging methods with various SEM sample preparation methods, i.e. chemical etching to extract the metal plug without inducing any damage to the metal, SEM cross section prepared with some oxide (about 1000A) left in front of the metal plug and standard SEM cross section through the metal plug. Complementary secondary and backscattered imaging has proven to be a reliable method for ascessing the filling of the contact holes. Wafer and package level reliability data for the planarized aluminum metallization used on a megabit device will also be presented.


international ieee vlsi multilevel interconnection conference | 1991

Reliability study of planarized aluminum metallization

H.H. Hoang; Fusen Chen; M. Zamanian; Girish Anant Dixit; Che-Chia Wei; Fu-Tai Liou

This work investigates the reliability issues associated with an aluminum process, called the Al-plug process, that results in the complete filling of submicron contacts and vias. It has been demonstrated that the Al-plug process is a viable means of filling high aspect ratio vias and contacts for submicron geometries and can be used without degrading device reliability. It also has been experimentally determined that the films microstructural parameters such as surface roughness, grain size, Si nodules and hillock formation are improved over the conventionally deposited Al-Si-Cu film. Both electromigration and stress-induced migration data also indicate that the Al-plug metal film is highly reliable. The planarity of the Al-Si-Cu lines in vias and over steps is excellent compared to that of a standard metal process.<<ETX>>


MRS Proceedings | 1991

Thermal Stability of Sputter Deposited Tantallum Silicide Films

Girish Anant Dixit; R. Sundaresan; Fusen Chen; Yih-Shung Lin; Che-Chia Wei; Fu-Tai Liou

Tantallum silicide films were sputter deposited from targets with different Si/Ta stoichiometries. The films were then subjected to thermal treatments. Silicon precipitation was observed on films deposited from silicon rich targets. The effects of silicon precipitates on device characteristics was studied. A method to suppress silicon precipitation is reported.


Archive | 1995

Method for forming a metal contact

Fusen E. Chen; Fu-Tai Liou; Yih-Shung Lin; Girish Anant Dixit; Che-Chia Wei


Archive | 1990

Method for fabricating interlevel contacts

Fusen E. Chen; Fu-Tai Liou; Timothy Edward Turner; Che-Chia Wei; Yih-Shung Lin; Girish Anant Dixit


Archive | 1992

Method for forming barrier metal layers

Girish Anant Dixit; Fu-Tai Liou; Che-Chia Wei; Fusen Chen


Archive | 1995

Semiconductor contact via structure

Yih-Shung Lin; Lun-Tseng Lu; Fu-Tai Liou; Che-Chia Wei; John L. Walters

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