Che-Fu Liang

A Digital Calibration Technique for Charge Pumps in Phase-Locked Systems

A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked systems. In this digital calibration technique, there is no extra replica CP needed. In addition, it can calibrate the CP under different control voltages on the loop filter to be immune to the channel-length modulation. Due to the digital nature, the additional power consumption and digital switching noise from the calibration circuits are turned off once the calibration is finished. A 5 GHz frequency synthesizer is used to justify the proposed calibration technique. The measured output spur is suppressed by 5.35 dB at 5.2 GHz after the calibration circuits are active. The measured output spur levels are less than -68.5 dBc throughout the whole output frequency range. The measured phase noise is -110 dBc/Hz at an offset frequency of 1 MHz.

A 14-band Frequency Synthesizer for MB-OFDM UWB Application

A 14-band frequency synthesizer for UWB application is realized in a 0.18 mum CMOS process. It uses two PLLs and three mixers. The unwanted spurs due to frequency mixing are at least 35dB lower than the output carriers by using a quadrature divide-by-3 circuit and a 2-stage single-sideband mixer. The core circuit area is 1.5 mm2 and the power consumption is 160mW

Spur-Suppression Techniques for Frequency Synthesizers

A frequency synthesizer with two spur-suppression circuits has been fabricated in 0.18 mum CMOS technology. The chip area is 1.3 mm times 1.3 mm. The frequency synthesizer consumes 18.9 mW from a 1.8-V supply. Compared with the conventional frequency synthesizer without the spur-suppression circuit, the measured reference spur at 8 MHz is reduced by 18 dBc for the first spur-suppression circuit and 31 dBc for the second one. The measured switching time from 1792 to 1824 MHz is 27.89 mus within 20 ppm of the target frequency.

Multi-band burst-mode clock and data recovery circuit

A multi-band burst-mode clock and data recovery (BMCDR) circuit is presented. The available data rates are 2488.32 Mbps, 1244.16 Mbps, 622.08 Mbps, and 155.52 Mbps, which are specified in a gigabit-capable passive optical network (GPON) [1]. A half-rate and lowjitter gated voltage-controlled oscillator (GVCO) and a phase-controlled frequency divider are used to achieve the multi-band reception. The proposed BMCDR circuit has been fabricated in a 0.18 μm CMOS process. Its active area is 0.41 mm2 and consumes 70 mW including I/O buffers from a 1.8 V supply. key words: multi-band, burst-mode, clock and data recovery, voltagecontrolled oscillator

A 10Gbps Burst-Mode CDR Circuit in 0.18μm CMOS

A 10Gbps burst-mode clock and data recovery (CDR) circuit has been fabricated in 0.18mum CMOS technology. It recovers the input data and clock within 32 bits by using a gated voltage-controlled oscillator, a quadrature generator and a phase-aligning loop incorporating a half-rate bang-bang phase detector and a digital phase interpolator. The measured peak-to-peak jitter of the recovered clock is 10.44ps. The die area is 1.73 times 2.01 mm2 and draw 200mW from a 1.8V supply.

A 20/10/5/2.5Gb/s Power-scaling Burst-Mode CDR Circuit Using GVCO/Div2/DFF Tri-mode Cells

PON is one of the promising solutions for the last-mile communication systems. In PONs, the fast-locked CDR circuit must lock within tens of bit times once the data packets arrive. The so-called burst-mode CDR (BMCDR) circuits with gated VCOs (GVCOs) have been presented. To meet the requirements of different PON standards, a multi-band BMCDR circuit is very desirable. The conventional multi-band technique is realized by a GVCO with dividers. Since the GVCO has to operate at the highest speed, it dissipates a fixed power, even though only a low data rate is required. Furthermore, the dividers introduce extra time delays to reduce the sampling margin that may become an issue for high data rates. In this work, a 20/10/5/2.5Gb/s power-scaling BMCDR circuit is implemented in 90nm CMOS technology. It is aimed to scale the power of a BMCDR circuit for different data rates. To realize a power-scaling multi-band BMCDR circuit, a tri-mode cell can be configured as a GVCO, a divide-by-2 divider, or 2 DFFs. Moreover, improvements are made to address the problem associated with the extra time delays that reduce the sampling margin.

A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector

A jitter-tolerance-enhanced 10 Gb/s clock/data recovery (CDR) is presented. By using a gated-digital-controlled oscillator (GDCO), the proposed GDCO-based phase detector achieves a wide linear range and its jitter tolerance is enhanced without sacrificing the jitter transfer. It has been fabricated in 0.13 um CMOS technology and consumes 60 mW from a 1.5 V supply.

A Single-PLL UWB Frequency Synthesizer Using Multiphase Coupled Ring Oscillator and Current-Reused Multiplier

A single phase-locked loop (PLL) frequency synthesizer for a mode-1 multiband orthogonal frequency-division multiplexing (MB-OFDM) ultrawideband (UWB) system is realized in 0.13-mum CMOS. A current-reused multiply-by-1.5 circuit and a multiphase coupled ring oscillator are adopted to reduce the power consumption. For a 4.488-GHz signal, the measured image sideband is -40 dBc. The measured switching time from 3.342 to 4.488 GHz is 1.5 ns. The area is 0.85times0.9 mm2 and the power is 31.2 mW for a 1.2-V supply voltage.

A Fast-Switching Frequency Synthesizer for UWB Applications

A fast-switching frequency synthesizer is presented for ultra-wideband MB-OFDM applications. This synthesizer generates three frequency tones with 528 MHz spacing. By using single-sideband mixers with Q-enhancement bandpass filters and switched-cascode multiplexers, the sideband rejection is less than -30dB at least and the frequency switching time is less than 7ns. The chip has been fabricated in 0.18mum CMOS process and the area is 1.32mm2. It consumed 70mW from a 1.8V supply

A 2.5Gbps Burst-Mode Clock and Data Recovery Circuit

A 2.5Gbps burst-mode CDR circuit is fabricated in 0.18mum CMOS process. The data generator for this CDR circuit is presented with reduced hardware and low power dissipation. The tight timing budget of the clock generator is also relaxed. The bit error rate less than 10-12 is achieved for a PRBS of 231-1 with 500ppm frequency deviation. The area of the digital core is 0.36mm2 and the power of 33mW/port is achieved for a 1.8V supply