Jung-Yu Chang

A spur-reduction technique for a 5-GHz frequency synthesizer

A spur-reduction technique is presented to achieve low reference spurs for a 5-GHz frequency synthesizer. A dual-path control scheme incorporated with a pair of the proposed smoothed varactors reduces the gain of voltage-controlled oscillator to less than 15 MHz/V, attenuates the spurious tones, and shortens the simulated settling time by 56%. In, addition, a digital frequency-calibration circuit is used to enlarge the tuning range to overcome process variations. A 5-GHz frequency synthesizer has been fabricated for verification in a 0.18-mum CMOS process. It exhibits phase noise of -79 and -113 dBc/Hz at 10-kHz and 1-MHz offset, respectively. The reference spur level of -74 dBc is achieved by using a second-order loop filter. The overall tuning range is 16.3% and power consumption is 36 mW from a 1.8-V supply. The total switching time including digital frequency calibration takes no more than 110 mus

A 0.7-2-GHz self-calibrated multiphase delay-locked loop

A 0.7-2-GHz precise multiphase delay-locked loop (DLL) using a digital calibration circuit is presented. Incorporating with the proposed digital calibration circuit, the mismatch-induced timing error among multiphase clocks in the proposed DLL can be self-calibrated. When the calibration procedure is finished, the digital calibration circuit can be turned off automatically to save power dissipations and reduce noise generations. A start controlled circuit is proposed to enlarge the operating frequency range of the DLL. Both the start-controlled circuit and the calibration circuit require an external reset signal to ensure the correctness of the calibration after temperature,operating frequency, and power supply voltage are settled. This DLL with the digital calibration circuit has been fabricated in a 0.18-/spl mu/m CMOS process. The measured results show the DLL exhibits a lock range of 0.7-2 GHz while the peak-to-peak jitter and rms jitter is 18.9ps and 2.5 ps at 2 GHz, respectively. When the calibration procedure is completed and the DLL operates at 1 GHz, the maximum mismatch-induced timing error among multiphase clocks is reduced from 20.4 ps (7.34 degree) to 3.5 ps (1.26 degree).

Calcium Bioavailability of Nanonized Pearl Powder for Adults

The present study was aimed to evaluate the calcium bioavailability of pearl powder for humans. Both the nanonized pearl powder (NPP) and the micronized pearl powder (MPP) prepared by a dry grinder were tested. A group of healthy adults free from hyperthyroidism, hypercalcemia, and hypocalcemia were recruited as the subjects for oral administration with the pearl powder. The bioavailability was evaluated by the serum total calcium increment, the serum intact parathyroid hormone (iPTH) reduction, and the urine calcium/creatinine ratio increment in 6 h after administration. The results show better absorption and retention of calcium from NPP, as reflected with the shorter time elapsed before the maximum concentration of calcium appeared in the serum, higher iPTH reduction, more calcium absorption, and higher maximum calcium concentration (C(max)) in serum after ingestion, than that from MPP. We conclude that pearl powder is a beneficial source of calcium for adults and that nanonization improves its calcium bioavailability.

A DLL-Based Variable-Phase Clock Buffer

A variable-phase clock buffer that uses a delay-locked loop (DLL) is presented. The variable-phase clock is achieved by switching the multiphase outputs of the divider in the DLL. The output phase is adjustable in a step of where pi/n is the ratio of two voltage-controlled delay lines in the proposed circuit. The prototype has been fabricated in a 0.18- CMOS process to realize the output phases of 0deg, 90deg, 180deg, and 270deg. The corresponding measured phase error is 3.24deg, 3.46deg, 3.89deg, and 1.94deg, respectively. The measured root-mean-squared jitter is 1.81 ps. The clock buffer consumes 67 mW including I/O circuits from a single 1.8-V supply at 600 MHz.

A 2.4GHz CMOS Quadrature VCO for 2.4GHz WLAN/Bluetooth Applications

A 2.4GHz low-phase-noise and low-phase-error LC tank quadrature voltage controlled oscillator (QVCO) using the parasitic vertical BJT coupling and RC phase shifters is presented. Based on the proposed techniques, the proposed QVCO can simultaneously have low phase noise and low phase error. This QVCO circuit has been realized in a 0.18mum triple-well CMOS process and exhibits below 0.2deg phase error with phase noise of -105dBc/Hz at 100kHz offset frequency. The tuning range is 380MHz from 2.27GHz to 2.65GHz with control voltage from 0.3V to 1.8V. It consumes 5.4mW at each tank

A Single-PLL UWB Frequency Synthesizer Using Multiphase Coupled Ring Oscillator and Current-Reused Multiplier

A single phase-locked loop (PLL) frequency synthesizer for a mode-1 multiband orthogonal frequency-division multiplexing (MB-OFDM) ultrawideband (UWB) system is realized in 0.13-mum CMOS. A current-reused multiply-by-1.5 circuit and a multiphase coupled ring oscillator are adopted to reduce the power consumption. For a 4.488-GHz signal, the measured image sideband is -40 dBc. The measured switching time from 3.342 to 4.488 GHz is 1.5 ns. The area is 0.85times0.9 mm2 and the power is 31.2 mW for a 1.2-V supply voltage.

A frequency synthesizer for Mode-1 MB-OFDM UWB applications

A frequency synthesizer for Mode-1 MB-OFDM UWB applications is realized in 65nm CMOS. By using a delay-locked loop (DLL) and the proposed multiply-by-two circuit, the frequency synthesizer achieves the in-band spur of −40dBc for the three-band operation. The proposed multiply-by-2 circuit realizes the quadrature signals, and its input signals do not need the 50% duty cycle. A modified current-starving cell in a DLL is also proposed to reduce the supply noise sensitivity. The measured switching time from 3.342GHz to 4.488GHz is around 1.1ns. The area is 1.25×1.175mm2 with pads and the power is 19.2mW for 1.2V supply.

A 4-54GHz Static Frequency Divider with Back-Gate Coupling

A static frequency divider by using the back-gate coupling technique is presented. The proposed circuit has been fabricated in a 90 nm CMOS process. Driven by the differential signals, the measured operating frequency range of the conventional circuit is from 4 GHz to 48 GHz, while that of the proposed circuit is from 4GHz to 54GHz by choosing the same device size. The measurement result shows that the proposed static frequency divider improves the operating frequency range by 10% with only a little overhead. The maximum power consumption is 39.7 mW from a 1.5 V supply voltage.

A Phase-Locked Loop With Background Leakage Current Compensation

A background compensation method is presented to compensate the leakage current of MOS capacitors for phase-locked loops (PLLs) in nanoscale CMOS technology. A leakage detection circuit is used to adjust a voltage-controlled current source to compensate the leakage current. This PLL has been fabricated in 65-nm CMOS technology. With the background leakage current compensation, the measured peak-to-peak and rms jitters of this PLL at 1 GHz are 36 and 4.54 ps, respectively. Its power consumption is 8.4 mW for a 1.2-V supply voltage.

A 15–20GHz delay-locked loop in 90nm CMOS technology

A 15 GHz~20 GHz delay-locked loop (DLL) has been fabricated in 90 nm CMOS technology. It not only relaxes the speed requirement of the voltage-controlled delay line (VCDL), but also allows the VCDL not to operate at the highest frequency. When this DLL operates at 20 GHz, the measured root-mean-square and peak-to-peak jitters are 0.813 ps and 6.62 ps, respectively. The core area is 0.25times0.4 mm2 and the power consumption is 49 mW for 0.9 V supply.