Chen-Chien Li

A higher-k tetragonal HfO2 formed by chlorine plasma treatment at interfacial layer for metal-oxide-semiconductor devices

A tetragonal HfO2 (t-HfO2) with higher-k value and large band gap is investigated in this work. X-ray diffraction analysis shows a t-HfO2 can be formed by using Cl2 plasma treatment at the HfO2/Si interface after a post deposition annealing at 650 °C. The mechanisms of t-HfO2 formation can be attributed to the Si diffusion and oxygen vacancy generation which are formed by Cl2 plasma treatment. From the cross-sectional transmission electron microscope and capacitance-voltage measurement, the k value of this t-HfO2 is estimated to be about 35. The optical band gap value for t-HfO2 is similar to that of the monoclinic.

Improved Electrical Characteristics of Ge pMOSFETs With ZrO 2 /HfO 2 Stack Gate Dielectric

Electrical characteristics of Ge pMOSFETs with HfO₂, ZrO₂, ZrO₂/HfO₂, and HfZrO_x gate dielectrics are studied in this letter. A lower equivalent oxide thickness (EOT) is obtained in ZrO² device, which, however, has a higher interface trap density (D_it) due to its inferior dielectric/Ge interface. Interestingly, the Dit and sub-threshold swing of Ge pMOSFETs are clearly reduced by ZrO₂/HfO₂ stack gate dielectric. A peak hole mobility of 335 cm²/V-s is achieved in ZrO₂/HfO₂ device thanks to good dielectric/Ge interface. Furthermore, the EOT of ZrO₂/HfO₂ device is 0.62 nm, and the leakage current is 2 × 10^-3 A/cm². Therefore, a ZrO₂/HfO₂ stack gate dielectric is promising for Ge MOSFETs.

An Ultralow EOT Ge MOS Device With Tetragonal HfO 2 and High Quality Hf x Ge y O Interfacial Layer

A Ge MOS device with an ultralow equivalent oxide thickness of ~0.5 nm and acceptable leakage current of 0.5 A/cm2 is presented in this paper. The superior characteristics can be attributed to a tetragonal HfO2 with a higher k value (k ~ 31) and comparable bandgap. In addition, a Ge MOS device with tetragonal phase HfO2 (t-HfO2) also shows a lower leakage current and better thermal stability. The mechanisms for t-HfO2 formation may be explained by the little Ge diffusion from Ge substrate and oxygen deficiency, which are obtained by in situ interfacial layer (IL) formation and high-k processes. The IL with k ~ 13 can be formed by in situ H2O plasma treatment. Moreover, a Ge MOS device with the IL grown by H2O plasma shows smaller interface trap density and hysteresis effects due to a high composition of Ge+4.

Improved Electrical Characteristics of Ge MOS Devices With High Oxidation State in

Ge MOS devices with about 95% Ge4+ in HfGeOx interfacial layer are obtained by H2O plasma process together with in situ desorption before atomic layer deposition (ALD). The equivalent oxide thickness is scaled down to 0.39 nm; the leakage current is decreased as well. The improvement can be attributed to the in situ Ge suboxide desorption process in an ALD chamber at 370 °C. The interface trap density and frequency dispersion need further process development to be reduced.

{\rm HfGeO}_{\rm x}

Since the SiGe or Ge channel materials are desirable to enhance the carrier mobility degraded by ultrathin high-k gate dielectric, the pMOSFET device with novel superlattice (SL) SiGe channels is proposed in this letter. Experimental results show that the electrical characteristics of MOSFET can be obviously improved by an SL virtual substrate. The peak hole mobility of the pMOSFET device with SL is enhanced by about 100% as compared to that with the Si one. The on-off ratio of the Id-Vg curve is beyond eight orders, and the electrical thickness in inversion (Tinv) value of the gate dielectric can be ~1.4 nm. The source/drain activation temperature of 650°C is particularly suitable to high-k dielectric process.

Interfacial Layer Formed by In Situ Desorption

A stress-and-sense charge pumping (SSCP) technique is proposed in this paper to measure the stress-induced interface trap (ΔN_it) in real-time evolution without stress interruption. Results show that the ΔN_it measured by this SSCP technique is much higher than that measured by the conventional method. This difference is resulted from the recovery induced by stress interruption during the sensing measurements. The ΔN_it measured by SSCP method after interruption is approximately equal to that by the conventional one. The amount of recoverable ΔN_it is almost constant and independent of permanent damage. The stress-induced threshold voltage shift (ΔV_th) and ΔN_it under various stress frequencies and duty cycles are also measured. The ΔV_th seems to depend only on the total stress time of stress pulse. The ΔN_it measured by SSCP with different frequencies and duty cycles is similar. The ΔN_it also depends on the total stress time of stress pulse, but not the off time during the nonstress half cycle. In addition, it is found that the recovery induced by nonstress half cycle of ac stress is almost negligible as compared with that induced by stress interruption. Moreover, a two-stage phenomenon is observed on ΔN_it evolution. Results in this paper indicate that the stressing indeed induces trap generation in the first stage.

Enhanced Hole Mobility and Low

The HfO2 based insulator is promising for resistive random access memory (RRAM). At first in this work, the effects of different oxygen contents in sputtered HfO2 on resistive switching memory are investigated. It is observed that the oxygen flux rate would strongly affect the LRS/HRS current ratio and operation voltage. The switching behavior can be attributed to oxygen vacancy assisted conduction filament formation and annihilation. Then, the effects of Ti and Zr capping metal layers on RRAM devices with ALD-HfO2 insulator are studied. Resistive switching behavior, temperature-dependence retention, and cycling endurance are strongly affected by the property of capping metal layer.

Tinv

The TaN/HfON/GeO₂/n-Ge pMOSFETs were fabricated with different formation processes of GeO₂ interfacial layer. Ultra low EOT of around 0.5 nm is achieved using GeO₂ grown by H₂O plasma together with in-situ grown HfON gate dielectric, and simultaneously the peak hole mobility of Ge pMOSFET is 312 cm²/V*s.

for pMOSFET by a Novel Epitaxial Si/Ge Superlattice Channel

Abstract Ultralow equivalent oxide thickness and excellent reliability characteristics in Ge MOS devices with ZrO2 gate dielectrics are achieved by capping Hf or Zr on interfacial layer. Device with a Hf-cap layer demonstrates the lowest interface trap density and stress-induced leakage current. On the other hand, device with a Zr-cap layer exhibits the lowest hysteresis effects and stress-induced voltage shifts. The HfGeOx IL of high quality and ZrGeOx IL with few oxide traps are promising to improve reliability characteristics in Ge MOS devices.

Detection of Stress-Induced Interface Trap Generation on High-

The equivalent oxide thickness in Ge MOS device is scaled down to 0.39 nm, and the leakage current is decreased as well. The improvement can be attributed to the in-situ Ge sub-oxide desorption process in an ALD chamber at 370 ^°C. About 95% Ge⁴⁺ in HfGeO_x interfacial layer are obtained by H₂O plasma process together with in-situ desorption before atomic layer deposition.