Kuei-Shu Chang-Liao

Study of gate oxide traps in HfO2/AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors by use of ac transconductance method

We introduce an ac-transconductance method to profile the gate oxide traps in a HfO2 gated AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors (MOS-HEMTs) that can exchange carriers with metal gates, which in turn causes changes in analog and pulsed channel currents. The method extracts energy and spacial distributions of the oxide and interface traps under the gate from the frequency dependence of ac transconductance. We demonstrate the method using MOS-HEMTs with gate oxides that were annealed at different temperatures.

Charge-Trapping-Type Flash Memory Device With Stacked High-

Operating properties of charge-trapping-type Flash memory devices with single or stacked structures on trapping layer are investigated in this letter. Improved operation and reliability characteristics can be achieved by adapting the stacked high-k films as charge-trapping layer due to the modification in the trap density and the energy level of traps, the mechanism of electron/hole transmission, and the suitable band offset. Moreover, with a small bandgap of second film in the stacked trapping layer, operating characteristics of devices are further enhanced.

k

Satisfactory operation and reliability characteristics of SONOS-type flash devices are achieved by an optimal Hf/Al content in HfAlO charge-trapping layer. Results indicate that operation performance can be improved by a suitable band offset of HfAlO charge-trapping layer. High-speed operation can be realized by adopting CHEI programming and F-N erasing for NOR flash applications.

Charge-Trapping Layer

A polycrystalline silicon (poly-Si) channel twin thin-film transistor (twin-TFT) nonvolatile memory (NVM) device with In-Ga-Zn-O<i>x</i> (IGZO) as a storage layer is demonstrated. IGZO-FG twin-TFT NVM exhibits a large memory window Δ<i>V</i>_th. A <i>V</i>_CG at 18 V for 10 ms can achieve 5.6 V of Δ<i>V</i>_th. An extrapolation of the memory window to ten years demonstrates that the stored charge still remains 65% of its initial value. Coupling ratio effect and gate length effect are discussed in detail. Such a low-temperature IGZO-FG twin-TFT NVM device is feasible for integration in IGZO-based display circuits for system-on-panel applications.

Novel SONOS-Type Nonvolatile Memory Device with Suitable Band Offset in HfAlO Charge-Trapping Layer

Operation properties of polysilicon-oxide-nitride-oxide-silicon-type Flash device with HfAlO charge-trapping layer having various Al contents were investigated in this letter. Satisfactory performance in terms of operation speed, retention, and program/erase endurance of the Flash device is achieved with the optimal Al content of 18%-28% in the HfAlO trapping layer. In addition, high-speed operation can be attained with the combination of channel-hot-electron-injection programming and band-to-band hot hole erasing for NOR architecture applications.

Twin Thin-Film Transistor Nonvolatile Memory With an Indium–Gallium–Zinc–Oxide Floating Gate

A tetragonal HfO2 (t-HfO2) with higher-k value and large band gap is investigated in this work. X-ray diffraction analysis shows a t-HfO2 can be formed by using Cl2 plasma treatment at the HfO2/Si interface after a post deposition annealing at 650 °C. The mechanisms of t-HfO2 formation can be attributed to the Si diffusion and oxygen vacancy generation which are formed by Cl2 plasma treatment. From the cross-sectional transmission electron microscope and capacitance-voltage measurement, the k value of this t-HfO2 is estimated to be about 35. The optical band gap value for t-HfO2 is similar to that of the monoclinic.

Novel SONOS-Type Nonvolatile Memory Device With Optimal Al Doping in HfAlO Charge-Trapping Layer

Microstructure effect of Cu/low-k interconnect, which is substantially affected by process condition or manufacturing deviation, is a dominated factors for copper stress and critical to the formation of stress-induced voiding (SIV). In this work, SIV at via bottom is studied in the aspects of thickness variation of copper interconnect and low-k dielectric. Besides, via-related factors consist of via profile and dimension are also involved in SIV sensitivity studies. With the assistance of finite element analysis (FEA), Cu stress in terms of different Cu/low-k microstructure scenarios are modelled to understand the voiding evolution and explore the their dependence with SIV susceptibility. Meanwhile, microstructure effects with and without redundant via are also simulated to evaluate their impacts on SIV immunity.

A higher-k tetragonal HfO2 formed by chlorine plasma treatment at interfacial layer for metal-oxide-semiconductor devices

Charge-pumping (CP) technique is proposed to simultaneously measure the border traps and interface-trap density (Dit). The charge pumped per cycle (Qcp) versus high level (Vh ) of gate pulse for various frequencies was used to observe the behavior of the bulk traps close to the interface as a function of the CP frequency. Evolution on Qcp as a function of frequency was successfully used to determine the depth profile of border-trap density near the high-kappa gate dielectric/Si interface. The influence of border trap in high-kappa dielectric on the Dit measurement can be prevented by an appropriate selection of gate frequency in CP technique

A study of Cu/Low-k stress-induced voiding at via bottom and its microstructure effect

This work examined the effects of bulk nitrogen in HfOxNy gate dielectric on current-conduction and charge trapping of metal-oxide-semiconductor devices. The nitrogen concentration profiles in HfOxNy gate dielectric were adjusted by Hf target sputtered in an ambient of modulated nitrogen flow. The current-conduction mechanisms of HfOxNy film comprised of various nitrogen concentration profiles at the low- and high-electrical field were dominated by Schottky emission and Frenkel–Poole emission, respectively. The trap energy level involved in Frenkel–Pool conduction was estimated to be around 0.8 eV. Smaller stress-induced leakage current and flat-band voltage shift were obtained for devices with HfOxNy dielectric containing less bulk nitrogen, attributable to less interface strain∕stress and bulk trap.

Depth Profiling of Border Traps in MOSFET With High-

Plasma charging effects on the gate insulator of high-dielectric constant (k) material in MOS devices deserve to be investigated because of different trap-assisted conduction mechanisms. Plasma-induced degradation in gate-leakage current and time to breakdown is clearly observed in this work. MOS device with Si/sub 3/N/sub 4/ film seems to have smaller degradation of gate-leakage current while it suffers shorter time to breakdown as compared to Ta/sub 2/O/sub 5/ samples. For devices with Ta/sub 2/O/sub 5/ film, a larger physical thickness suffers more reliability degradation from plasma charging damage because of the richer traps. Thus, a smaller physical thickness of high-k dielectric film is favorable for sub-micron MOS devices of ULSI application.