Li-Jung Liu

Growth and Properties of Sputter-Deposited CuInS2 Thin Films

Abstract Single-phase CuInS 2 thin films were prepared by r.f. sputtering. The asdeposited films were p type with resistivities in the range 10 −1 −10 1 ω cm . X-ray and electron diffraction data are discussed. Rutherford backscattering and atomic absorption were used for analysis of the composition and the impurities in the thin films. Both the growth direction and the composition of the thin films could be varied by increasing the sulphur vapour pressure during sputtering. Grain size and resistivity data and the effects of post-deposition annealing are also presented.

Improved Electrical Characteristics of Ge pMOSFETs With ZrO 2 /HfO 2 Stack Gate Dielectric

Electrical characteristics of Ge pMOSFETs with HfO₂, ZrO₂, ZrO₂/HfO₂, and HfZrO_x gate dielectrics are studied in this letter. A lower equivalent oxide thickness (EOT) is obtained in ZrO² device, which, however, has a higher interface trap density (D_it) due to its inferior dielectric/Ge interface. Interestingly, the Dit and sub-threshold swing of Ge pMOSFETs are clearly reduced by ZrO₂/HfO₂ stack gate dielectric. A peak hole mobility of 335 cm²/V-s is achieved in ZrO₂/HfO₂ device thanks to good dielectric/Ge interface. Furthermore, the EOT of ZrO₂/HfO₂ device is 0.62 nm, and the leakage current is 2 × 10^-3 A/cm². Therefore, a ZrO₂/HfO₂ stack gate dielectric is promising for Ge MOSFETs.

An Ultralow EOT Ge MOS Device With Tetragonal HfO 2 and High Quality Hf x Ge y O Interfacial Layer

A Ge MOS device with an ultralow equivalent oxide thickness of ~0.5 nm and acceptable leakage current of 0.5 A/cm2 is presented in this paper. The superior characteristics can be attributed to a tetragonal HfO2 with a higher k value (k ~ 31) and comparable bandgap. In addition, a Ge MOS device with tetragonal phase HfO2 (t-HfO2) also shows a lower leakage current and better thermal stability. The mechanisms for t-HfO2 formation may be explained by the little Ge diffusion from Ge substrate and oxygen deficiency, which are obtained by in situ interfacial layer (IL) formation and high-k processes. The IL with k ~ 13 can be formed by in situ H2O plasma treatment. Moreover, a Ge MOS device with the IL grown by H2O plasma shows smaller interface trap density and hysteresis effects due to a high composition of Ge+4.

Improved Electrical Characteristics of Ge MOS Devices With High Oxidation State in

Ge MOS devices with about 95% Ge4+ in HfGeOx interfacial layer are obtained by H2O plasma process together with in situ desorption before atomic layer deposition (ALD). The equivalent oxide thickness is scaled down to 0.39 nm; the leakage current is decreased as well. The improvement can be attributed to the in situ Ge suboxide desorption process in an ALD chamber at 370 °C. The interface trap density and frequency dispersion need further process development to be reduced.

{\rm HfGeO}_{\rm x}

Since the SiGe or Ge channel materials are desirable to enhance the carrier mobility degraded by ultrathin high-k gate dielectric, the pMOSFET device with novel superlattice (SL) SiGe channels is proposed in this letter. Experimental results show that the electrical characteristics of MOSFET can be obviously improved by an SL virtual substrate. The peak hole mobility of the pMOSFET device with SL is enhanced by about 100% as compared to that with the Si one. The on-off ratio of the Id-Vg curve is beyond eight orders, and the electrical thickness in inversion (Tinv) value of the gate dielectric can be ~1.4 nm. The source/drain activation temperature of 650°C is particularly suitable to high-k dielectric process.

Interfacial Layer Formed by In Situ Desorption

The operation characteristics of p-channel TaN/ Al₂O₃/HfO₂/HfAlO₂/SiO₂/Si MAHOS-type nonvolatile memory devices with different Ge contents in a SiGe buried channel are investigated in this letter. Compared with those of a device having a conventional Si-channel, both programming and erasing speeds are significantly improved by employing a Si_0.7Ge_0.3 buried channel. Satisfactory retention and excellent endurance characteristics up to 10⁶ P/E cycles with 4.1-V memory window show that the degradation on reliability properties, if it exists, is negligible when the SiGe buried channel is introduced.

Enhanced Hole Mobility and Low

The HfO2 based insulator is promising for resistive random access memory (RRAM). At first in this work, the effects of different oxygen contents in sputtered HfO2 on resistive switching memory are investigated. It is observed that the oxygen flux rate would strongly affect the LRS/HRS current ratio and operation voltage. The switching behavior can be attributed to oxygen vacancy assisted conduction filament formation and annihilation. Then, the effects of Ti and Zr capping metal layers on RRAM devices with ALD-HfO2 insulator are studied. Resistive switching behavior, temperature-dependence retention, and cycling endurance are strongly affected by the property of capping metal layer.

Tinv

Operation characteristics in a polycrystalline silicon (poly-Si) nanowire (NW) charge-trapping (CT) flash memory device are studied with SiGe buried channel for the first time. Compared with the flash device with a general poly-Si NW channel, the device with SiGe buried channel shows improved programming and erasing speeds since the enhanced electric field in tunneling layer is enhanced by SiGe buried layer. The endurance characteristics are also improved by the SiGe buried channel while retention performances are retained. The SiGe buried channel is promising to CT flash device for 3D nonvolatile memory applications.

for pMOSFET by a Novel Epitaxial Si/Ge Superlattice Channel

The TaN/HfON/GeO₂/n-Ge pMOSFETs were fabricated with different formation processes of GeO₂ interfacial layer. Ultra low EOT of around 0.5 nm is achieved using GeO₂ grown by H₂O plasma together with in-situ grown HfON gate dielectric, and simultaneously the peak hole mobility of Ge pMOSFET is 312 cm²/V*s.

Enhanced Programming and Erasing Speeds in P-Channel Charge-Trapping Flash Memory Device With SiGe Buried Channel

Charge-trapping (CT) flash memory devices with Ge channel are studied for the first time. The operation characteristics of Ge-channel devices with different interfacial layers (IL), including GeO2, GeON, and AlON, are investigated. The programming/erasing speeds of devices with Ge channel can be significantly improved as compared with those with Si or SiGe channel. The retention properties of Ge-channel CT flash devices are much enhanced with a stacked tunneling layer formed by the low-temperature processes. However, the endurance characteristics of Ge-channel devices need improvement as compared with those of Si-channel devices. This may be resolved by a high-quality IL formed with an electron cyclotron resonance system and passivated with a H2 treatment.