Chendong Zhu

Damage mechanisms in impact-ionization-induced mixed-mode reliability degradation of SiGe HBTs

A robust, time-dependent methodology is used to investigate impact-ionization-induced mixed-mode reliability stress (the simultaneous application of high J/sub E/ and high V/sub CB/) in advanced SiGe HBTs. We present comprehensive stress data on second-generation 120-GHz SiGe HBTs, and use specially designed test structures with variable emitter-to-shallow trench spacing to shed light on the resultant damage mechanisms. We also explore the impact of mixed-mode stress on low frequency noise, ac performance, high-temperature device characteristics, and employ two-dimensional calibrated MEDICI simulations using the hot carrier injection current technique to better understand the physical damage locations.

SiGe BiCMOS Precision Voltage References for Extreme Temperature Range Electronics

We present the first investigation of the optimal implementation of SiGe BiCMOS precision voltage references for extreme temperature range applications (+120 degC to -180 degC and below). We have developed and fabricated two unique Ge profiles optimized specifically for cryogenic operation, and for the first time compare the impact of Ge profile shape on precision voltage reference performance down to -180 degC. Our best case reference achieves a 28.1 ppm/ degC temperature coefficient over +27 degC to -180 degC, more than adequate for the intended lunar electronics applications

A High-Slew Rate SiGe BiCMOS Operational Amplifier for Operation Down to Deep Cryogenic Temperatures

We investigate, for the first time, the design and implementation of a high-slew rate op-amp in SiGe BiCMOS technology capable of operation across very wide temperature ranges, and down to deep cryogenic temperatures. We achieve the first monolithic op-amp (for any material system) capable of operating reliably down to 4.3 K. Two variants of the SiGe BiCMOS op-amp were implemented using alternative biasing schemes, and the effects of temperature on these biasing schemes, and their impact on the overall op-amp performance, is investigated

Impact of Scaling on the Inverse-Mode Operation of SiGe HBTs

The inverse-mode operational regime of silicon germanium (SiGe) heterojunction bipolar transistors (HBTs) has to date been largely ignored and is typically dismissed as a viable possibility for circuit applications due to the general perception of its limited dc and ac performance capabilities. In this paper, the inverse-mode performance of four distinct generations of SiGe HBTs is investigated and is found to improve impressively with generational scaling. The physics behind these scaling-induced improvements is examined in detail using a combination of measurements and calibrated simulations. A novel lateral dependence of the inverse-mode base current is identified and is shown to potentially present new opportunities for even larger improvements in inverse-mode performance in SiGe HBTs. A record peak fT in inverse mode of 25 GHz is reported for a prototype fourth-generation device

Assessing reliability issues in cryogenically-operated SiGe HBTs

We assess SiGe HBTs for emerging mixed-signal cryogenic circuits designed to operate on the Moon without ambient heating or cooling (from +120C to as low as -230C), focusing of potential reliability issues. Comprehensive mixed-mode reliability stress data for these SiGe HBTs were measured from 300 K to 85 K. We extract the thermal resistance over temperature to evaluate the impact of the self-heating at low temperatures, explore the low-frequency noise performance at room temperature and cryogenic temperatures as a function of stress condition, and examine the impact of cooling on breakdown voltage and operating point instabilities for mixed-signal circuits.

A New Current-Sweep Method for Assessing the Mixed-Mode Damage Spectrum of SiGe HBTs

We present a new ldquocurrent-sweeprdquo stress methodology for quantitatively assessing the mixed-mode reliability (simultaneous application of high current and high voltage) of advanced silicon-germanium (SiGe) HBTs. This electrical-stress methodology allows one to quickly obtain the complete ldquodamage spectrumrdquo of a given device from a particular technology platform, enabling better understanding of the complex voltage, current, and temperature interdependence associated with electrical stress and burn-in of advanced transistors. We consistently observe three distinct regions of mixed-mode damage in SiGe HBTs and find that hot-carrier-induced damage can be introduced into SiGe HBTs under surprisingly modest mixed-mode-stress conditions. For more aggressively scaled technology generations, a larger percentage of hot carriers generated in the collector-base junction are able to travel to and hence damage the emitter-base (EB) spacer, leading to enhanced forward-mode base-current leakage under stress. A new self-heating-induced mixed-mode-annealing effect is observed for the first time under specific high-voltage- and high-current-stress conditions, and a new damage mechanism is observed under very high-voltage and high-current conditions. Finally, as an example of the utility of our stress methodology, we quantify the composite mixed-mode damage spectrum of a commercial third-generation (200 GHz) SiGe HBT. We find that if devices are stressed with either voltage or current alone during burn-in, they can easily withstand extreme overstress conditions. Unfortunately, devices can easily be damaged when stressed with a combination of stress voltage and current, and this has significant implications for the lifetime prediction under realistic mixed-signal-circuit operating conditions.

CMOS Device Reliability for Emerging Cryogenic Space Electronics Applications

0C (43K) in the polar shadows), makes operation of the electronics sub-systems on the surface of the Moon exceptionally difficult, but is nonetheless required for the envisioned complex suite of electronics systems used in sensing, actuation, and control of robotic systems. Such applications are typically fairly low frequency in nature (e.g., < 100 MHz), hence not requiring the most aggressively scaled CMOS technology; however, a full suite of mixed-signal circuit building blocks, and reliable operation of those circuits across extremely large variations in temperature (e.g., +120 to -230C) is needed. Adequate device reliability must clearly be achieved to accomplish this task. CMOS device degradation due to hot carriers effect (HCE) is known to be considerably worse at low temperatures [2]. Device lifetime data at cryogenic temperatures, and a solid understanding of the corresponding degradation mechanisms, are thus critical in this context of space electronics, and are addressed in this work. The Si CMOS devices investigated here are from an advanced 0.5µm SiGe BiCMOS technology, with a fixed channel width of 10.0 µm, and effective gate lengths ranging from 0.35 µm (minimum geometry), to 5.0 µm. The devices were characterized on a custom cryogenic probe system from 300K down to 43 K (-230 0 C). For brevity we will focus on the nFET data, since it represents the worst case in this technology. Fig. 1 and 2 shows typical I-V characteristics for the CMOS devices at different temperatures. The current drive capability increases significantly for the same bias conditions, as the temperature decreases. The nFET lifetime was inferred using stress-induced changes to the ID-VG characteristics. The lifetime τ is defined here as the inferred stress time for which a certain parameter of the ID-VG characteristics has shifted by a predefined amount (e.g., 10% degradation of gm). A typical lifetime assessment analysis using the ID-VG characteristics for a 1.0 µm nFET are shown in Fig. 3 and Fig. 4. The slope of 0.6 for the linear fitting in Fig. 4 suggests that interface state generation is responsible for the observed device degradation at the maximum substrate current (VG ≈ ½ VD); while that of 0.3 for the maximum gate current bias condition (VG = VD) suggests that oxide trapped charge dominates [3]. For the nFETs operating at 300K, the worst case bias condition for hot carrier degradation is known to be under maximum substrate current bias. There has been speculation that the worst case bias conditions for hot carrier degradation can, however, be a function of temperature [4]. It can be verified from Fig. 4 that for this technology, maximum substrate current is indeed the worst bias condition, at least down to 82K, and hence was the condition used here for device lifetime evaluation. The substrate current is comprised of the generated hot carriers, and is thus a good monitoring parameter for HCE in practical measurements. Fig. 5 and Fig. 6 show the effects of temperature and gate length on substrate current, respectively. It can be seen from Fig. 5 that the maximum substrate current under the same bias condition increases by 3x as temperature decreases from 300K to 43K; while Fig. 6 suggests that the maximum substrate current increases by more than 10x as L shrinks from 1.0 µm to 0.35 µm, and becomes negligible as L increases to 5.0 µm. This suggests that HCE is impacted more by device geometry than by the temperature. Fig. 7 shows the inferred lifetime at different drain bias’ at different temperatures. As seen in Fig. 7, τ decreases by ~10x as the temperature is reduced from 300K to 82K. Furthermore, τ differs by more than 100x between the 1.0 µm and 0.35/5 µm transistors, and hence the longer-channel devices are preferred for cryogenic applications of this technology Assuming fast interface trap generation dominates the HCE degradation, plotting τID versus ISUB/ID on a log-log scale should yield a straight line behavior [5]. The critical electron energy for generating an interface trap is calculated to be 3.9 eV from the slop of the line. Both the slope and the critical energy from Fig. 8 correlate well with literature data (2.9 and 3.7 eV in [5]), suggesting that interface state generation is the dominant limiting reliability factor at low temperatures.

An Investigation of Negative Differential Resistance and Novel Collector–Current Kink Effects in SiGe HBTs Operating at Cryogenic Temperatures

In this paper, a new negative-differential-resistance (NDR) effect and a novel collector-current kink effect are investigated in the cryogenically operated SiGe heterojunction bipolar transistors (HBTs). Theory based on an enhanced positive-feedback mechanism associated with heterojunction barrier effect at deep cryogenic temperatures is proposed to explain both the observed NDR and the collector-current kink. The accumulated charge induced by the barrier effect acts at low temperatures to enhance the total collector-current, indirectly producing both phenomena. This theory is confirmed using the calibrated 2-D DESSIS simulations over temperature. These unique cryogenic effects also have significant impact on the ac performance of SiGe HBTs operating at high injection. Technology evolution plays an important role in determining the magnitude of the observed phenomena, and the scaling implications are addressed. In addition, the present NDR effect is also compared with previously reported NDR and hysteresis effects observed in highly scaled SiGe HBTs operating under forced-IB-base bias. The input drive condition of the transistor during its use in circuits, either under pure forced-current bias or under pure forced-voltage bias, or more practically, somewhere in between, determines the magnitude of the observed NDR and is of potential concern for circuit designers and must be carefully modeled

SiGe Profile Optimization for Improved Cryogenic Operation at High Injection

This paper explores SiGe profile optimization for improved cryogenic operation at high injection. Through analyzing distributive transit time profiles, the bottle neck limiting high injection fT is identified and then eliminated in an optimized profile design. The fabricated profile indeed shows considerably improved fT and beta at high injection

Temperature Scalable Modeling of SiGe HBT DC Currents Down to 43K

Of critical importance to successful circuit design is accurate device models. At present, designers of electronics for extreme environment electronics are using the same device models used by general purpose electronics designers, which only work between -55◦C to 120◦C. In some cases, the temperature dependences of device parameters are turned off, and device parameters are extracted to only fit measured data at a single temperature. One may repeat this for several temperature points to obtain “isothermal” model parameters. Clearly this approach does not allow self-heating. More importantly, such models cannot be used to design circuits that require continuous description of device performance over temperature [1], such as the bandgap reference circuit, a fundamental circuit block critical to reliable operation over a wide range of temperature of numerous analog, digital, and mixed-signal circuits. This work presents improved equations for the collector and base currents, with an emphasis on lower temperature operation down to 43 K.