Guofu Niu

A new "mixed-mode" reliability degradation mechanism in advanced Si and SiGe bipolar transistors

A new mixed-mode base current degradation mechanism is identified in bipolar transistors for the first time, which, at room temperature, induces a large I/sub B/ leakage current only after simultaneous application of both high J/sub C/ and high V/sub CB/. This new mechanism differs fundamentally from well-known I/sub B/ degradation mechanisms such as the reverse EB voltage stress, high forward current stress and damage due to ionizing radiation. Extensive measurements and two-dimensional (2-D) simulations have been used to help understand the device physics associated with this new degradation mechanism.

A unified approach to RF and microwave noise parameter modeling in bipolar transistors

A unified approach to RF and microwave noise parameter modeling in bipolar transistors is presented. Circuit level noise parameters including the minimum noise figure, the optimum generator admittance, and the noise resistance are analytically linked to the fundamental noise sources and the y-parameters of the transistor through circuit analysis of the chain noisy two-port representation. Comparisons of circuit level noise parameters from different physical models of noise sources in the transistor were made against measurements in UHV/CVD SiGe HBTs. A new model for the collector shot noise is then proposed which produces better noise parameter agreement with measured data than the SPICE noise model and the thermodynamic noise model, the two most recent Y-parameter based noise models.

A total resistance slope-based effective channel mobility extraction method for deep submicrometer CMOS technology

A simple yet effective total resistance slope-based method for extracting the effective channel mobility in deep submicrometer CMOS technology is developed. Using the slope of the measured total resistance versus mask length, the series resistance is removed from the measured total resistance, and mobility is extracted without involving the effective channel length. The new method facilitates mobility extraction in situations where the effective channel length is difficult to extract, such as in lightly-doped-drain (LDD) devices or at low temperatures. The new method also allows the series resistance to be any function of the gate bias, making the mobility extraction in LDD devices easier and more accurate.

RF linearity characteristics of SiGe HBTs

Two-tone intermodulation in ultrahigh vacuum/chemical vapor deposition SiGe heterojunction bipolar transistors (HBTs) were analyzed using a Volterra-series-based approach that completely distinguishes individual nonlinearities. Avalanche multiplication and collector-base (CB) capacitance were shown to be the dominant nonlinearities in a single-stage common emitter amplifier. At a given I/sub c/ an optimum V/sub ce/ exists for a maximum third-order intercept point (IIP3). The IIP3 is limited by the avalanche multiplication nonlinearity at low I/sub c/, and limited by the C/sub CB/ nonlinearity at high I/sub c/. The decrease of the avalanche multiplication rate at high I/sub c/ is beneficial to linearity in SiGe HBTs. The IIP3 is sensitive to the biasing condition because of strong dependence of the avalanche multiplication current and CB capacitance on I/sub c/ and V/sub ce/. The load dependence of linearity was attributed to the feedback through the CB capacitance and the avalanche multiplication in the CB junction. Implications on the optimization of the transistor biasing condition and transistor structure for improved linearity are also discussed.

Design and fabrication of planar guard ring termination for high-voltage SiC diodes

Abstract An optimized multiple floating guard ring structure is investigated for the first time as an edge termination method for high voltage 4H-SiC planar devices. Simulations were performed to investigate SiC guard ring termination, and determine the optimum guard ring spacing for planar diodes with up to four floating rings. Simulated optimized designs predicted breakdown values from 40% of the ideal breakdown with a single ring, to 84% of the ideal value for diodes with four rings. Implanted 4H-SiC pn diodes with optimized guard ring designs were fabricated and results correlated to simulation. Experimental breakdown values of 1.2–1.3 kV for guard ring structure with four rings were in good agreement with simulated results.

Optimization of SiGe HBTs for operation at high current densities

A comprehensive investigation of the impact of Ge profile shape as well as the scaling of collector and base doping profiles on high-injection heterojunction barrier effects in SiGe HBTs has been conducted over the -73-85/spl deg/C temperature range. The onset of Kirk effect at high current densities is shown to expose the Si/SiGe heterojunction in the collector-base space charge region, thereby inducing a conduction band barrier which negatively impacts the collector and base currents as well as the dynamic response, leading to a premature roll-off in both /spl beta/ and f/sub T/. In light of this, careful profile optimization is critical for emerging SiGe HBT circuit applications, since they typically operate at high current densities to realize maximum performance. We first explore the experimental consequences and electrical signature of these barrier effects over the 200-358 K temperature range for a variety of Ge profiles from an advanced UHV/CVD SiGe HBT technology. We then use extensive simulations which were calibrated to measured results to explore the sensitivity of these barrier effects to both the Ge profile shape and collector profile design, and hence investigate the optimum profile design points as a function of vertical scaling.

An investigation of the origins of the variable proton tolerance in multiple SiGe HBT BiCMOS technology generations

This paper presents the first investigation of the physical origins of the observed variable proton tolerance in multiple SiGe HBT BiCMOS technology generations. We use the combination of an extensive set of newly measured proton data on distinct SiGe HBT BiCMOS technology generations, detailed calibrated 2-D MEDICI simulations for both the SiGe HBT and Si CMOS devices, as well as reverse-bias emitter-base and forward-bias electrical stress data to aid the analysis. We find that the scaling-induced increase in the emitter-base electric field under the spacer oxide in the SiGe HBT is primarily responsible for the degraded radiation tolerance with technology scaling, while the decrease in shallow-trench thickness is largely responsible for the improved nFET radiation tolerance with technology scaling.

Autonomous bit error rate testing at multi-gbit/s rates implemented in a 5AM SiGe circuit for radiation effects self test (CREST)

SEE testing at multi-Gbit/s data rates has traditionally involved elaborate high speed test equipment setups for at-speed testing. We demonstrate a generally applicable self test circuit approach implemented in IBMs 5AM SiGe process, and describe its ability to capture complex error signatures during circuit operation at data rates exceeding 5 Gbit/s. Comparisons of data acquired with FPGA control of the CREST ASIC versus conventional bit error rate test equipment validate the approach. In addition, we describe SEE characteristics of the IBM 5AM process implemented in five variations of the D flip-flop based serial register. Heavy ion SEE data acquired at angles follow the traditional RPP-based analysis approach in one case, but deviate by orders on magnitude in others, even though all circuits are implemented in the same 5AM SiGe HBT process.

Noise in SiGe HBT RF Technology: Physics, Modeling, and Circuit Implications

This paper presents an overview of the physics, modeling, and circuit implications of RF broad-band noise, low-frequency noise, and oscillator phase noise in SiGe heterojunction bipolar transistor (HBT) RF technology. The ability to simultaneously achieve high cutoff frequency (f/sub T/), low base resistance (r/sub b/), and high current gain (/spl beta/) using Si processing underlies the low levels of low-frequency 1/f noise, RF noise, and phase noise of SiGe HBTs. We first examine the RF noise sources in SiGe HBTs and the RF noise parameters as a function of SiGe profile design, transistor biasing, sizing, and operating frequency, and then show a low-noise amplifier design example to bridge the gap between device and circuit level understandings. We then examine the low-frequency noise in SiGe HBTs and develop a methodology to determine the highest tolerable low-frequency 1/f noise for a given RF application. The upconversion of 1/f noise, base resistance thermal noise, and shot noises to phase noise is examined using circuit simulations, which show that the phase noise corner frequency in SiGe HBT oscillators is typically much smaller than the 1/f corner frequency measured under dc biasing. The implications of SiGe profile design, transistor sizing, biasing, and technology scaling are examined for all three types of noises.

Heavy-ion broad-beam and microprobe studies of single-event upsets in 0.20-/spl mu/m SiGe heterojunction bipolar transistors and circuits

Combining broad-beam circuit level single-event upset (SEU) response with heavy ion microprobe charge collection measurements on single silicon-germanium heterojunction bipolar transistors improves understanding of the charge collection mechanisms responsible for SEU response of digital SiGe HBT technology. This new understanding of the SEU mechanisms shows that the right rectangular parallel-piped model for the sensitive volume is not applicable to this technology. A new first-order physical model is proposed and calibrated with moderate success.