Ramkumar Krithivasan

Half-terahertz operation of SiGe HBTs

This letter presents the first demonstration of a silicon-germanium heterojunction bipolar transistor (SiGe HBT) capable of operation above the one-half terahertz (500 GHz) frequency. An extracted peak unity gain cutoff frequency (f/sub T/) of 510 GHz at 4.5 K was measured for a 0.12/spl times/1.0 /spl mu/m/sup 2/ SiGe HBT (352 GHz at 300 K) at a breakdown voltage BV/sub CEO/ of 1.36 V (1.47 V at 300 K), yielding an f/sub T//spl times/BV/sub CEO/ product of 693.6 GHz-V at 4.5 K (517.4 GHz-V at 300 K).

An investigation of the origins of the variable proton tolerance in multiple SiGe HBT BiCMOS technology generations

This paper presents the first investigation of the physical origins of the observed variable proton tolerance in multiple SiGe HBT BiCMOS technology generations. We use the combination of an extensive set of newly measured proton data on distinct SiGe HBT BiCMOS technology generations, detailed calibrated 2-D MEDICI simulations for both the SiGe HBT and Si CMOS devices, as well as reverse-bias emitter-base and forward-bias electrical stress data to aid the analysis. We find that the scaling-induced increase in the emitter-base electric field under the spacer oxide in the SiGe HBT is primarily responsible for the degraded radiation tolerance with technology scaling, while the decrease in shallow-trench thickness is largely responsible for the improved nFET radiation tolerance with technology scaling.

Autonomous bit error rate testing at multi-gbit/s rates implemented in a 5AM SiGe circuit for radiation effects self test (CREST)

SEE testing at multi-Gbit/s data rates has traditionally involved elaborate high speed test equipment setups for at-speed testing. We demonstrate a generally applicable self test circuit approach implemented in IBMs 5AM SiGe process, and describe its ability to capture complex error signatures during circuit operation at data rates exceeding 5 Gbit/s. Comparisons of data acquired with FPGA control of the CREST ASIC versus conventional bit error rate test equipment validate the approach. In addition, we describe SEE characteristics of the IBM 5AM process implemented in five variations of the D flip-flop based serial register. Heavy ion SEE data acquired at angles follow the traditional RPP-based analysis approach in one case, but deviate by orders on magnitude in others, even though all circuits are implemented in the same 5AM SiGe HBT process.

Heavy-ion broad-beam and microprobe studies of single-event upsets in 0.20-/spl mu/m SiGe heterojunction bipolar transistors and circuits

Combining broad-beam circuit level single-event upset (SEU) response with heavy ion microprobe charge collection measurements on single silicon-germanium heterojunction bipolar transistors improves understanding of the charge collection mechanisms responsible for SEU response of digital SiGe HBT technology. This new understanding of the SEU mechanisms shows that the right rectangular parallel-piped model for the sensitive volume is not applicable to this technology. A new first-order physical model is proposed and calibrated with moderate success.

An SEU hardening approach for high-speed SiGe HBT digital logic

A new circuit-level single-event upset (SEU) hardening approach for high-speed SiGe HBT current-steering digital logic is introduced and analyzed using both device and circuit simulations. The workhorse D-type flip-flop circuit architecture is modified in order to significantly improve its SEU immunity. Partial elimination of the effect of cross-coupling at the transistor level in the storage cell of this new circuit decreases its vulnerability to SEU. The SEU response of this new circuit is quantitatively compared with three other D flip-flop architectures, including the unhardened circuit, a conventional NAND gate based circuit, and a current-sharing hardened (CSH) circuit, at both variable data rate and switching current. The new circuit shows substantial improvement in SEU response over the unhardened version, with little increase in layout complexity and power consumption. While the NAND gate based circuit still shows better SEU response than the other circuits, its high power consumption will preclude its use in space applications. Our results suggest that this new circuit architecture exhibits sufficient SEU tolerance, low layout complexity, and modest power consumption, and thus should prove suitable for many space applications requiring very high-speed digital logic.

On the Performance Limits of Cryogenically Operated SiGe HBTs and Its Relation to Scaling for Terahertz Speeds

The goal of achieving terahertz (THz) transistors within the silicon material system has generated significant recent interest. In this paper, we use operating temperature as an effective way of gaining a better understanding of the performance limits of SiGe HBTs and their ultimate capabilities for achieving THz speeds. Different approaches for vertical profile scaling and reduction of parasitics are addressed, and three prototype fourth-generation SiGe HBTs are compared and evaluated down to deep cryogenic temperatures, using both dc and ac measurements. A record peak fT/fmax of 463/618 GHz was achieved at 4.5 K using 130-nm lithography (309/343 GHz at 300 K), demonstrating the feasibility of reaching half-THz fT and fmax simultaneously in a silicon-based transistor. The BVCEO of this cooled SiGe HBT was 1.6 V at 4.5 K (BVCBO = 5.6 V), yielding a record fT times BVCEO product of 750 GHzldrV (510 GHzldrV at 300 K). These remarkable levels of transistor performance and the associated interesting device physics observed at cryogenic temperatures in these devices provide important insights into further device scaling for THz speeds at room temperature. It is predicted in a new scaling roadmap that fT/fmax of room-temperature SiGe HBTs could potentially achieve 782/910 GHz at a BVCEO of 1.1 V at the 32-nm lithographic node.

Application of RHBD Techniques to SEU Hardening of Third-Generation SiGe HBT Logic Circuits

Shift registers featuring radiation-hardening-by-design (RHBD) techniques are realized in IBM 8HP SiGe BiCMOS technology. Both circuit and device-level RHBD techniques are employed to improve the overall SEU immunity of the shift registers. Circuit-level RHBD techniques include dual-interleaving and gated-feedback that achieve SEU mitigation through local latch-level redundancy and correction. In addition, register-level RHBD based on triple-module redundancy (TMR) versions of dual-interleaved and gated-feedback cell shift registers is also realized to gauge the performance improvement offered by TMR. At the device-level, RHBD C-B-E SiGe HBTs with single collector and base contacts and significantly smaller deep trench-enclosed area than standard C-B-E-B-C devices with dual collector and base contacts are used to reduce the upset sensitive area. The SEU performance of these shift registers was then tested using heavy ions and standard bit-error testing methods. The results obtained are compared to the unhardened standard shift register designed with CBEBC SiGe HBTs. The RHBD-enhanced shift registers perform significantly better than the unhardened circuit, with the TMR technique proving very effective in achieving significant SEU immunity

A comparison of SEU tolerance in high-speed SiGe HBT digital logic designed with multiple circuit architectures

The single-event upset (SEU) responses of three D flip-flop circuits, including two unhardened, and one current-sharing hardened (CSH) circuit, are examined using device and circuit simulation. The circuit that implements the conventional D flip-flop logic using standard bipolar NAND gates shows much better SEU performance than the other two. Cross coupling at transistor level in the storage cell of the other two circuits increases their vulnerability to SEU. The observed differences are explained by analyzing the differential output of the emitter coupled pair being hit. These results suggest a potential path for achieving sufficient SEU tolerance in high-speed SiGe heterojunction bipolar transistor (HBT) digital logic for many space applications.

Substrate Engineering Concepts to Mitigate Charge Collection in Deep Trench Isolation Technologies

Delayed charge collection from ionizing events outside the deep trench can increase the SEU cross section in deep trench isolation technologies. Microbeam test data and device simulations demonstrate how this adverse effect can be mitigated through substrate engineering techniques. The addition of a heavily doped p-type charge-blocking buried layer in the substrate can reduce the delayed charge collection from events that occur outside the deep trench isolation by almost an order of magnitude, implying an approximately comparable reduction in the SEU cross section

Proton radiation response of SiGe HBT analog and RF circuits and passives

Presents the first experimental results of the effects of 63 MeV proton irradiation on SiGe heterojunction bipolar transistor (HBT) analog and radio-frequency (RF) circuits and passive elements. A SiGe HBT bandgap, reference circuit, commonly used to generate stable on-chip voltages in analog ICs, a SiGe HBT voltage-controlled oscillator, a key building block for RF transceivers, and an LC bandpass filter routinely used in RF circuit design were each irradiated to proton fluences as high as 5/spl times/10/sup 13/ p/cm/sup 2/. The degradation associated with these extreme proton fluences was found to be minimal, suggesting that SiGe HBT technology is robust for these types of circuit applications.