Cheng-An Chien

A high throughput in-loop de-blocking filter supporting H.264/AVC BP/MP/HP video coding

This paper presents a high throughput VLSI architecture for H.264/AVC in-loop de-blocking filter (ILF) supporting baseline, main, and high profile (BP/MP/HP) video decoding targeted at HDTV applications. We develop a 4times4/8times8 filter and a buffer management scheme to perform the various coding tools in H.264 de-blocking filter for supporting the coding tools of picture adaptive frame/field (PAFF) coding, macroblock adaptive frame/field (MBAFF) coding, and 8times8 transform coding. In particular, we adopt two local buffers to store the reference MB pair data and reschedule the internal pixels when switching the filtering operations on the horizontal and vertical edges without writing it out to the external memory. Adopting TSMC 0.13 mum CMOS technology, we implement the proposed design with the cost of 36.9 K gates and 672 bytes of local memory when operating at 225 MHz. Moreover, the proposed design achieves the data throughput rate of 260 cycles per MB in average, which meets the real-time processing requirement for H.264 16 VGA (2560times1920)@30 fps video decoding.

Low complexity 3D depth map generation for stereo applications

In this paper we propose a low complexity algorithm to generate 3D image depth map in good quality based on a single 2D image for stereo applications. Owing to the different characteristics of images, the 2-D images are first classified into three categories and then processed by the proposed low complexity techniques to generate the depth map. With good quality in the generated depth map, we achieve about 90% in complexity reduction using the proposed algorithm, which is beneficial to real-time realization through hardware or software implementation for the stereo applications.

A high throughput deblocking filter design supporting multiple video coding standards

This paper presents a high throughput, VLSI architecture for multi-standard in-loop deblocking filter (ILF) supporting H.264 BP/MP/HP, AVS, and VC-1 video decoding. It comprises 38.4Kgates and 672bytes of local memory using TSMC 0.13µm CMOS technology when operating at 225 MHz which meets the real-time processing requirement for high-resolution video decoding. We develop a PDB scheme and an integrated 1-D filter to realize various coding tools of the deblocking filter supporting multiple video coding standards.

A 360-degree panoramic video system design

In this paper, a low-complexity video stitching algorithm and its system prototype are proposed. With the novel design, users can obtain a high-resolution, high quality and seamless 360-degree panoramic video immediately by stitching the images with overlapped regions. Most of the present works are focused on image stitching instead of video stitching. In the proposed design, we develop some novel methods to solve the problems encountered in video stitching. First, we provide a new blending method to remove the color difference in video stitching. Moreover, we avoid the moving objects in the overlapped area by using the dynamic seam adjustment scheme. Finally, we remove the drift problem and obtain a better visual quality while displaying the 360 degree panoramic video scenes. The implementation results show that the entire system achieves 4-channel D1 30fps real-time video stitching on an Intel i7 3930K CPU 2.3GHz machine with 8GB DDR3 memory and Linux Ubuntu 12.10 operation system.

Unsteady thermosolutal opposing convection of a liquid-water mixture in a square cavity. I: Flow formation and heat and mass transfer characteristics

Abstract Transient thermosolutal opposing convection of a liquid-water mixture in a square cavity subject to horizontal temperature and concentration gradients is numerically investigated by a third-order upwind finite-difference scheme. Results are particularly presented to illustrate the effects of the Lewis and Grashof numbers on the evolution of flow patterns and the associated heat and mass transfer characteristics for solutally dominant situations. Results for Le = 100 clearly show the double-diffusive nature of the convection. In the initial stage the flow is dominated by the interface velocities at the vertical side walls driven by the concentration gradients there. Later, the flow is governed by the thermal buoyancy. At a much later time, the solutal buoyancy set in inducing new recirculating cells along the side walls. These cells gradually grow and squeeze the thermally driven cell in the core region. Multilayer flow structure is finally formed. The counterrotating cells resulting from the opposing thermal and solutal buoyancies cause significant velocity, temperature and concentration oscillations with time at high Grashof numbers.

A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS

This paper presents a video recording SoC fabricated in 65nm low-power technology, which integrates a complexity and bandwidth-effective H.264 encoder, an ultra-low-power (ULP) MPU, with timing-optimized ROM and 8T SRAM macros for ultra-low-voltage (ULV) operation, a 512Kb ULV and leakage-aware 8T SRAM for the frame buffer (FB), and various on-chip peripherals, such as external memory interfaces (Fig. 9.3.1). Utilizing ULV cell libraries with custom-pulsed D flip-flops (PFF) for wide-range voltage scaling, ROM/SRAM macros optimized simultaneously for timing and leakage, and advanced energy management (AEM), the SoC achieves 32fps HD720 H.264 encoding at 1.0V, down to 0.57nJ/pixel ultra-low energy dissipation at 0.48V (30fps QQVGA H.264 encoding for preview through ANT+).

Multi-core software/hardware co-debug platform with ARM CoreSight™, on-chip test architecture and AXI/AHB bus monitor

Multi-core system is becoming the next generation embedded design platform. Heterogeneous and homogeneous processor cores integrated in Multiple Instruction Multiple Data (MIMD) System-on-a-Chip (SoC) to provide complex services, e.g. smart phones, is coming up in the horizon. However, distributed programming is a difficult problem in such systems. Today, only in very few MIMD SoC designs we can find comprehensive multi-core software/hardware co-debug capability that can stop at not only software but also hardware breakpoints to inspect data and system status for identifying bugs. In this work we have integrated various debug mechanisms so that the entire multi-core SoC is able to iterate unlimited times of software and hardware breaks for data and status inspections and stepping forward to resume execution till next break point. This debug mechanism is realized with a chip with four ARM1176 cores and ARM CoreSight™ on-chip debug and trace system, a Field Programmable Gate Array (FPGA) loaded with on-chip test architecture and bus monitor, and software debug platform to download system trace and processor core data for inspection and debug control. Key contributions of this work are (1) a development of multi-clock multi-core software/hardware co-debug platform and (2) the exercise of a multi-core program debugging to visualize the physical behavior of race conditions.

A low-complexity image stitching algorithm suitable for embedded systems

In this paper we propose a low-complexity image stitching algorithm. By using the developed algorithm, users can automatically merge images into a panoramic image, even these source images have rotation and zooming actions. We adopt feature-base estimation to get the relation between images and employ down-sampling to reduce computing complexity. We also apply a copy-paste and texture-base scheme to remove the clear seam in the result image. Realized in an embedded system with 512MHz RISC, the proposed algorithm could achieve a XVGA image stitching in 0.6 second.

A two level mode decision algorithm for H.264 high profile intra encoding

A two level mode decision algorithm considering edge information for H.264 high profile intra encoding is proposed to reduce the computational complexity. In level one mode decision, the edge information is used to decide the appropriate intra coding block size according to the observations that a smooth macroblock usually chooses the large intra coding block size, and that a complex macroblock usually chooses the small one. In level two mode decision, we use the correlation between adjacent blocks to decide the appropriate prediction modes. The proposed method achieves 34%~59% reduction of computational complexity when compared to JM14 and the PSNR only drops 0.09 db in average.

A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video

This paper proposes a dual mode video decoder with 4-level temporal/spatial scalability and 32/64-bit adjustable memory bus width. A design automation environment for simulation and verification is established to automatically verify the correctness and completeness of the proposed design. Using a 0.13 um CMOS technology, it comprises 439Kgates/10.9KB SRAM and consumes 2∼328mW in decoding CIF∼HD1080 videos at 3.75∼30fps when operating at 1∼150MHz, respectively.