Cheng-Kuan Yin

New heterogeneous multi-chip module integration technology using self-assembly method

We have newly proposed heterogeneous multi-chip module integration technologies in which MEMS and LSI chips are mounted on Si or flexible substrates using a self-assembly method. A large numbers of chips were precisely and simultaneously self-assembled and bonded onto the substrates with high alignment accuracy of approximately 400 nm. Thick MEMS and LSI chips with a thickness of more than 100 mum were electrically connected by unique lateral interconnections formed crossing over chip edges with large step height. We evaluated fundamental electrical characteristics using daisy chains formed crossing over test chips which were face-up bonded onto the substrates by the self-assembly. We obtained excellent characteristics in these daisy chains. In addition, RF test chips with amplitude shift keying (ASK) demodulator and signal processing circuits were self-assembled onto the substrates and electrically connected by the lateral interconnections. We confirmed that these test chips work well.

MOSFET Nonvolatile Memory with High-Density Cobalt-Nanodots Floating Gate and

We report high-performance MOSFET nonvolatile memory with high-density cobalt-nanodots (Co-NDs) floating gate (the density is as high as 4-5 × 1012 /cm 2 and the size is ~2 nm) and HfO2 high-k blocking dielectric. The device is fabricated using a gate-last process. A large memory window, high-speed program/erase (P/E), long retention time, and excellent endurance till 106 P/E cycles are obtained. In addition, the discrete Co-NDs make dual-bit operation successful. The high performance suggests that high work-function Co-NDs combined with high-k blocking dielectric have a potential as a next-generation nonvolatile-memory candidate.

\hbox{HfO}_{\bf 2}

In this letter, cobalt nanodots (Co-NDs) had been formed via a self-assembled nanodot deposition. High resolution transmission electron microscopy and x-ray photoelectron spectroscopy analyses clearly show that the high metallic Co-ND is crystallized with small size of ∼2 nm and high density of (4–5)×1012/cm2. The metal-oxide-semiconductor device with high density Co-NDs floating gate and high-k HfO2 blocking dielectric exhibits a wide range memory window (0–12 V) due to the charge trapping into and distrapping from Co-NDs. After 10 years retention, a large memory window of ∼1.3 V with a low charge loss of ∼47% was extrapolated. The relative longer data retention demonstrates the advantage of Co-NDs for nonvolatile memory application.

High-k Blocking Dielectric

In this letter, the formation of high density tungsten nanodots (W-NDs) embedded in silicon nitride via a self-assembled nanodot deposition is demonstrated. In this method, tungsten and silicon nitride are cosputtered in high vacuum rf sputtering equipment. The W-NDs with small diameters (1–1.5 nm) and high density (∼1.3×1013/cm2) were achieved easily by controlling W composition; this is the ratio of total area of W chips to that of silicon nitride target. The metal-oxide-semiconductor memory device was fabricated with high density W-NDs floating gate and high-k HfO2 blocking dielectric. A wide range memory window (0–29 V) was obtained after bidirectional gate voltages sweeping with range of ±1–±23 V. It is feasible to design the memory window with propriety power consumption for nonvolatile memory application.

Memory characteristics of metal-oxide-semiconductor capacitor with high density cobalt nanodots floating gate and HfO2 blocking dielectric

Fe50Pt50 nanodots dispersed in a SiO2 film (Fe50Pt50 nanodot film) were formed by a self-assembled nanodot deposition (SAND) method in which Fe50Pt50 and SiO2 are cosputtered in a high vacuum rf magnetron sputtering equipment. Fe50Pt50 pellets are laid on a SiO2 target in a sputtering chamber to form the Fe50Pt50 nanodot film in the SAND method. The size and density of Fe50Pt50 nanodot were controlled by changing the ratio of the total area of Fe50Pt50 pellets to that of SiO2 target. The Fe50Pt50 nanodot size decreases and its density increases when the ratio decreases. As-deposited Fe50Pt50 nanodots self-assembled to a face-centered-cubic phase of single-crystal structure. The Fe50Pt50 nanodot films were annealed to evaluate the nanodot size controllability, the magnetic anisotropy, and the thermal stability. Fully ordered L10 face-centered-tetragonal Fe50Pt50 nanodots with high magnetocrystalline anisotropy (Ku≅8.7×107ergs∕cm3) were obtained by in situ annealing at 600°C for 1h in a high vacuum ambience...

Formation of high density tungsten nanodots embedded in silicon nitride for nonvolatile memory application

The chemical states of Fe and Pt in in situ annealed L10 structured FePt nanodots formed by self-assembled nanodot deposition method have been systematically investigated by angle resolved x-ray photoelectron spectroscopy. From the Fe3p and the Pt4f core level x-ray photoelectron (XP) spectra, it is evident that both the Fe and Pt of the nanodots were oxidized in the as-grown state. After the in situ annealing under high vacuum, a peak corresponding to metallic Fe begins to appear, and subsequently the metallic peak fraction increased with the increase in the annealing temperature. In line with this, the peak fraction of the respective oxides is drastically decreased. Irrespective of the annealing temperatures, it is inferred from the intensity of the XP spectrum that the Fe atom of the FePt nanodots is highly prone to oxidation than the Pt atom. Nevertheless, the valence band spectra of the as-grown FePt nanodot film clearly depict the presence of metallic Fe–Pt alloy. We would like to explain the result...

Magnetic properties of FePt nanodots formed by a self-assembled nanodot deposition method

A new magnetic nanodot (MND) memory with FePt nanodots was proposed. The FePt nanodots dispersed in SiO2 insulating film was successfully fabricated by self-assembled nanodot deposition (SAND). The size of the FePt nanodot can be controlled by SAND with a different target area ratio of the FePt pellets area in the SiO2 target. Thermal annealing converts the magnetic properties of the FePt nanodots from antiferromagnetic into high coercivity ferromagnetic without thermal agglomeration. An L10 face-centered tetragonal (fct) FePt MND film was successfully formed which acted as a charge retention layer. Furthermore, the fundamental characteristics of the MND memory were investigated using magnetic metal oxide semiconductor (MOS) capacitor devices.

Investigation of the effect of in situ annealing of FePt nanodots under high vacuum on the chemical states of Fe and Pt by x-ray photoelectron spectroscopy

A novel flash memory which has FePt magnetic floating gate was proposed. An FePt magnetic floating gate with a high coercivity was successfully fabricated by DC magnetron sputtering with rapid thermal annealing. As for magnetic properties, the switching magnetic fields of 21 Oe for the NiFe film and 1600 Oe for the FePt film were employed for the control gate and the floating gate materials, respectively. The fundamental characteristics of the magnetic flash memory were confirmed using magnetic metal oxide semiconductor (MOS) capacitor devices and magnetic tunneling diode (MTD) devices.

New Magnetic Nanodot Memory with FePt Nanodots

Metal-oxide-semiconductor field-effect transistor (MOSFET) nonvolatile memories with high-density tungsten nanodots (W-NDs) dispersed in silicon nitride as a floating gate were fabricated and characterized. The W-NDs with a high density of ~5 × 1012 cm−2 and small sizes of 2–3 nm were formed by self-assembled nanodot deposition (SAND). A large memory window of ~1.7 V was observed with bi-directional gate voltage sweeping between −10 and +10 V. Considering that there is no hysteresis memory window for the reference sample without W-NDs, this result indicates the charge trapping in W-NDs or related defects. Finally, the program/erase speed and retention characteristics were investigated and discussed in this paper.

New Magnetic Flash Memory with FePt Magnetic Floating Gate

Japan Sci. and Technol. Agency (JST), Tohoku Univ., Dept. of Bio-Engg. and Robotics, 6-6-01 Aza-Aoba, Aramaki, Aoba-ku, Sendai 980-8579, Japan Musashi Inst. Technol., Dept. of Electrical and Electronics Engg., 1-28-1 Tamazutumi, Tokyo 158-8557, Japan JASRI/SPring-8, Sayo-gun, Hyogo 679-5198 Japan Musashi Inst. Technol., Res. Ctr. Silicon Nano Sci., Setagaya-ku, 8-15-1 Todoroki, Tokyo 1580082, Japan Tohoku Univ., Inst. for Materials Res., Katahira 2-1-1, Aoba-ku, Sendai, Miyagi 980-8577, Japan Kyushu Univ., Dept. of Electronics, Fukuoka 812-8581, Japan Phone:+81-22-795-6906, Fax:+81-22-795-6907, E-mail: murugesh@sd.mech.tohoku.ac.jp