Jichel Bea

Evaluation of Cu Diffusion From Cu Through-Silicon Via (TSV) in Three-Dimensional LSI by Transient Capacitance Measurement

The influence of Cu contamination from Cu through-silicon via (TSV) on device reliability in the 3-D LSI has been electrically evaluated by capacitance-time (C-t) measurement. The Cu/Ta gate trench capacitors with two types of Ta barrier layers of 10- and 100-nm thicknesses (at the surface) were fabricated. The C-t curves of the trench capacitors with 100-nm-thick Ta layer exhibit no change after annealing up to 60 min at 300 °C. However, the C-t curves of the trench capacitors with 10-nm-thick Ta layer were severely degraded even after the initial annealing for 5 min. It means that Cu atoms diffuse into the active area from the Cu TSV through scallop portions with extremely thin Ta layer in TSVs, and consequently, the generation lifetime of minority carrier is significantly reduced. The C-t analysis is a useful method to electrically characterize the influence of Cu contamination from the Cu TSV on device reliability in fabricated LSI wafers.

Evaluation of Cu Contamination at Backside Surface of Thinned Wafer in 3-D Integration by Transient-Capacitance Measurement

The influence of Cu contamination at backside surface of a thinned wafer in three-dimensional LSI was electrically evaluated by capacitance-time (C-t) measurement. A MOS capacitor was fabricated using a thinned wafer of 50-μm thickness. The (C-t) curves of the MOS capacitor were severely degraded even after initial annealing at 300 °C for 5 min. It means that Cu atoms at the back surface reach the Si-SiO2 interface of the front surface, and the generation lifetime is significantly reduced. The quantitative relationship between the generation lifetime and surface concentration of Cu atom was evaluated. The (C-t) measurement is a highly promising method to electrically characterize the influence of Cu contamination on device reliability in fabricated LSI wafers.

Impact of Cu diffusion from Cu through-silicon via (TSV) on device reliability in 3-D LSIs evaluated by transient capacitance measurement

The influence of Cu contamination from Cu through-silicon via (TSV) on device reliability in the 3-D LSI was electrically evaluated by capacitance-time (C-t) measurement. The Cu/Ta gate trench capacitors with two types of Ta barrier layers of 10-nm and 100-nm thicknesses (at the wafer surface) were fabricated. The C-t curves of the trench capacitors with 10-nm thick Ta layer were severely degraded even after the initial annealing for 5min. It means that Cu atoms diffuse into the active area from the Cu TSV through scallop portions with extremely thin Ta layer in TSVs, and consequently, the generation lifetime of minority carrier is significantly reduced. Meanwhile, the C-t curves of the trench capacitors with 100-nm thick Ta layer exhibit no change after annealing up to 60min at 300°C, but show significant degradation after the initial annealing for 5min at 400°C. The C-t analysis is a useful method to electrically characterize the influence of Cu contamination from the Cu TSV on device reliability in fabricated LSI wafers.

Impacts of Cu Contamination on Device Reliabilities in 3-D IC Integration

The impacts of Cu contamination from a backside surface of a thinned wafer and Cu via on device reliabilities in 3-D IC integration are electrically evaluated. Intrinsic gettering (IG) layer, which was formed by high density oxygen precipitate, shows excellent Cu retardation characteristics from the backside surface of the thinned wafer. Extrinsic gettering (EG) layer, which was formed by postgrinded dry polish (DP) treatment shows good Cu retardation characteristics compared with other postgrinded treatments. The minimal 30-nm-thick Ta barrier layer in Cu via shows good barrier property to Cu diffusion from Cu via after annealing up to 60 min at 300 °C. However, it is not enough at 400 °C annealing, because the generation lifetime shows significant degradation after the initial annealing for 5 min. The DRAM cell characteristics show severe shortening retention time after an intentional Cu diffusion from the backside of the thinned DRAM chip at relatively low temperature of 300 °C.

New Magnetic Nanodot Memory with FePt Nanodots

A new magnetic nanodot (MND) memory with FePt nanodots was proposed. The FePt nanodots dispersed in SiO2 insulating film was successfully fabricated by self-assembled nanodot deposition (SAND). The size of the FePt nanodot can be controlled by SAND with a different target area ratio of the FePt pellets area in the SiO2 target. Thermal annealing converts the magnetic properties of the FePt nanodots from antiferromagnetic into high coercivity ferromagnetic without thermal agglomeration. An L10 face-centered tetragonal (fct) FePt MND film was successfully formed which acted as a charge retention layer. Furthermore, the fundamental characteristics of the MND memory were investigated using magnetic metal oxide semiconductor (MOS) capacitor devices.

Novel Hybrid Bonding Technology Using Ultra-High Density Cu Nano-Pillar for Exascale 2.5D/3D Integration

We propose a novel hybrid bonding technology with a high stacking yield using ultra-high density Cu nanopillar (CNP) for exascale 2.5D/3D integration. To solve the critical issues of a current standard hybrid bonding technology, we developed scaled electrodes with slightly extruded structure and unique adhesive layer of anisotropic conductive film composed of ultra-high density CNP. Test element group (TEG) dies with 7-mm × 23-mm size are bonded to interposer wafer by a new hybrid bonding technology. Scaled electrodes with 3-μm diameter and 6-μm pitch are formed in each TEG chip. We confirmed for the first time that a huge number of electrodes of 4309200 are successfully connected in series with the joining yield of 100% due to the ultra-high density CNP.

Impacts of Cu contamination in 3D integration process on memory retention characteristics in thinned DRAM chip

The influences of Cu contamination on 3D DRAM memory cell retention are characterized for Cu migration from the ground backside surface of a chip and Cu filled TSVs. The DRAM cell retention characteristics in chips thinned to 50-μm thickness then CMP polished are dramatically degraded, regardless of the well structure, after intentional Cu diffusion from the grinded backside surface at 300°C, 30 min. Meanwhile, the retention characteristics of DRAM cell in the thinned DRAM chip, which was DP-treated, is not degraded even after annealing. The retention characteristics of some memory cells separated by 20-μm ~ 50-μm from arrays of 10-μm diameter Cu TSVs began to degrade after post-annealing at 300°C, 30 min owing to the in-sufficient blocking property of the sputtered-Ta barrier layers in TSV array. The CVD Mn oxide layer formed as a barrier layer in the TSVs shows better barrier property results compared with the sputtered Ta barrier layer.

New Magnetic Flash Memory with FePt Magnetic Floating Gate

A novel flash memory which has FePt magnetic floating gate was proposed. An FePt magnetic floating gate with a high coercivity was successfully fabricated by DC magnetron sputtering with rapid thermal annealing. As for magnetic properties, the switching magnetic fields of 21 Oe for the NiFe film and 1600 Oe for the FePt film were employed for the control gate and the floating gate materials, respectively. The fundamental characteristics of the magnetic flash memory were confirmed using magnetic metal oxide semiconductor (MOS) capacitor devices and magnetic tunneling diode (MTD) devices.

Characterization and reliability of 3D LSI and SiP

Reliability challenges in 3D LSI associated with mechanical constraints induced by Cu TSVs, μ-bumps and crystal defects, crystallinity in thinned Si wafer and metal contamination induced by Cu diffusion from TSVs and thinned backside surface are mainly discussed. Mechanical stresses induced by Cu TSVs and μ-bumps are strongly dependent on design rules and process parameters. DRAM retention characteristics were severely degraded by Si thinning, especially below 30 μm thickness. Minority carrier lifetime was seriously degraded by Cu diffusion from Cu TSVs as the blocking property of barrier layer in TSV is not sufficient. A dry polish (DP) treatment produced a superior extrinsic gettering (EG) layer to Cu diffusion at the backside. We suggest the nondestructive failure analysis using X-ray CT-scan to characterize TSVs connection and μ-bumps joining in 3D stacked LSIs.

3D Integration technologies using self-assembly and electrostatic temporary multichip bonding

We developed a new chip-to-wafer 3D integration technology using self-assembly and electrostatic (SAE) bonding. High-throughput multichip self-assembly with a high alignment accuracy within 1 μm was achieved by the SAE bonding technique. Self-assembled known good dies (KGDs) were temporarily bonded on SAE carriers by electrostatic bonding force. We implemented multichip transfer processes twice and then formed through-silicon vias (TSVs) for the self-assembled KGDs to fabricate 3D-stacked chips with Cu-TSVs and Cu/SnAg microbumps. By using the new multichip-to-wafer 3D integration process with SAE bonding, we obtained good electrical characteristics from the self-assembled KGDs having Cu-TSVs and Cu/SnAg microbumps.