J. C. Bea

Surface tension-driven chip self-assembly with load-free hydrogen fluoride-assisted direct bonding at room temperature for three-dimensional integrated circuits

We have demonstrated fluidic chip self-assembly on Si wafers for fabricating three-dimensional integrated circuits. In this self-assembly technique, small droplets of hydrofluoric acid were employed to simultaneously align many millimeter-scale chips and directly bond them to the hydrophilic bonding areas formed on the host wafers by oxide–oxide bonding. The liquid surface tension enables many Si chips to be self-assembled with the highest alignment accuracy of 50 nm. In addition, many chips were tightly bonded to the hydrophilic bonding areas without applying a mechanical force after the liquid was evaporated at room temperature.

Wafer thinning, bonding, and interconnects induced local strain/stress in 3D-LSIs with fine-pitch high-density microbumps and through-Si vias

Mechanical strain/stress and crystal defects are produced in extremely thin wafers (thickness ∼10 µm) of 3D-LSIs not only during wafer thinning, but also after wafer bonding using fine-pitch, high-density microbumps and curing. Furthermore, the metal of through-Si via (TSV) and microbump not only becomes the cause of contamination, but also induces strain/stress (due to the difference in the co-efficient of thermal expansion (CTE) between Si and metal) in thinned Si substrate. X-ray photoelectron spectroscopy (XPS) results showed that the crystal quality of Si is highly deteriorated in the ultra-poly ground (UPG) surface after wafer thinning and stress relief. Micro-Raman spectroscopy (µRS) data revealed that a local tensile strain amount to 1.8 GPa was induced by 4×4 µm2 square sized Si microbumps in 10 µm-thick LSI wafers after bonding and curing. We have noticed that this locally induced strain/stress caused more than 10% change in the ON current of p-MOS transistor. CuSn microbumps have also induced strain/stress at Si wafer surface, and it penetrates deeper for larger bump size and wider for smaller bump pitch.

New heterogeneous multi-chip module integration technology using self-assembly method

We have newly proposed heterogeneous multi-chip module integration technologies in which MEMS and LSI chips are mounted on Si or flexible substrates using a self-assembly method. A large numbers of chips were precisely and simultaneously self-assembled and bonded onto the substrates with high alignment accuracy of approximately 400 nm. Thick MEMS and LSI chips with a thickness of more than 100 mum were electrically connected by unique lateral interconnections formed crossing over chip edges with large step height. We evaluated fundamental electrical characteristics using daisy chains formed crossing over test chips which were face-up bonded onto the substrates by the self-assembly. We obtained excellent characteristics in these daisy chains. In addition, RF test chips with amplitude shift keying (ASK) demodulator and signal processing circuits were self-assembled onto the substrates and electrically connected by the lateral interconnections. We confirmed that these test chips work well.

Impact of remnant stress/strain and metal contamination in 3D-LSIs with through-Si vias fabricated by wafer thinning and bonding

Wafer thinning and formation of through-Si via (TSV) and metal microbump are key processes in 3D LSI fabrication. However, it might introduce mechanical stress and crystal defects in thinned wafers. In addition, Cu for TSV and microbump might introduce metal contamination in thinned Si substrate. Then the impact of mechanical stress and metal contamination in the thinned Si substrate has been investigated. The remnant stress left after wafer thinning was evaluated by micro-Raman spectroscopy (µRS) and XPS. It was found that the mechanical stress remained in the back surface of Si substrate after wafer thinning and a part of this mechanical stress appeared in the surface of Si substrate. The metal contamination in such thinned Si substrate has been evaluated by a C-t method. It was found that the carrier generation lifetime was degraded by Cu diffused into Si substrate at relatively low temperature of 200 °C. The mechanical stress/strain in the thinned Si substrate after wafer bonding was also evaluated to investigate the influences of metal microbumps to the thinned Si substrate. It was found that the local mechanical stress was generated in the Si substrate surface by the microbumps. This local stress caused a 3% change in the ON current of MOS transistor.

Multichip-to-Wafer Three-Dimensional Integration Technology Using Chip Self-Assembly With Excimer Lamp Irradiation

Self-assembly of multichips with metal microbump electrodes is demonstrated by using water surface tension to increase the stacking throughput/yield and chip alignment accuracy of conventional chip-to-wafer 3-D integration. Three-dimensional microbump interconnects are formed by self-assembly with thermal compression at 200°C. Chips with In-Au microbumps with pitches of 10 and 20 μm are tightly bonded to Si wafers after the flip-chip self-assembly process, resulting in high alignment accuracies of 0.8 and 0.2 μm in the x - and y-directions, respectively. Selective hydrophilization by 172-nm excimer lamp irradiation gives a high wettability contrast between hydrophilic chip bonding areas and hydrophobic surrounding areas on the wafers. This assists high-precision multichip self-assembly. A 2500-In-Au-microbump daisy chain is formed with a yield of 100% by flip-chip self-assembly, and it exhibits ohmic contact. The resistance is sufficiently low for 3-D large-scale integration application, being comparable to that obtained by conventional mechanical chip alignment.

10 µm fine pitch Cu/Sn micro-bumps for 3-D super-chip stack

We develop novel micro-bumping technology to realize small size, fine pitch and uniform height Cu/Sn bumps. Electroplated-evaporation bumping (EEB) technology, which is a combination of Cu electroplating and Sn evaporation, is developed to achieve uniform height of Cu/Sn bumps. We develop CMOS compatible dry etching processes for removing sputtered Cu/Ta layers to achieve small size and fine pitch Cu/Sn bump. 5 µm square and 10 µm pitch Cu/Sn micro-bumps are successfully fabricated for the first time. Bump height variation is 5 µm ±3 % (95%, 2σ), which is uniform compared to electroplated Cu/Sn bumps. We evaluate micro-joining characteristics of Cu/Sn micro-bumps. Good I–V characteristics are measured from the daisy chain consisting of 1500 bumps with 10 µm square and 20 µm pitch. Resistance of Cu/Sn bump is 35 mΩ/bump, which is very low value compared to electroplated Cu/Sn bumps.

Multichip Self-Assembly Technology for Advanced Die-to-Wafer 3-D Integration to Precisely Align Known Good Dies in Batch Processing

An advanced die-to-wafer 3-D integration using a surface-tension-driven multichip self-assembly technology was proposed to 3-D stack a large number of known good dies (KGDs) in batch processing. The parallel self-assembly with a unique multichip pick-up tool was newly applied to die-to-wafer 3-D integration to overcome throughput and yield problems in conventional 3-D integration approaches. In addition, novel batch transfer of chips self-assembled on a carrier wafer to the corresponding target wafer was demonstrated. By using the multichip self-assembly, many KGDs can be precisely aligned and temporarily placed on a carrier wafer all at once, and then, the self-assembled KGDs can be simultaneously transferred to another target wafer in a face-to-face bonding manner at the wafer level. Average alignment accuracy was found to be approximately 400 nm when a hundred 3-mm-square chips were self-assembled on carrier wafers with small droplets of an aqueous solution. The alignment accuracy was experimentally proven to be fairly dependent on liquid surface tension as a self-assembly parameter. The liquid wettability contrast between the chip assembly areas and the surrounding areas formed on carrier wafers was another key parameter for alignment accuracy. The former and the latter areas were rendered high hydrophilic and hydrophobic. These areas, respectively, showed water contact angles less than 5° and 115°. Therefore, various sizes of chips (3 × 3 mm, 5 × 5 mm, 4 × 9 mm, and 10 × 10 mm) were self-assembled on a carrier wafer with high alignment accuracy, and further, the self-assembled chips were successfully transferred to the other faced target wafer in a batch.

Reconfigured-Wafer-to-Wafer 3-D Integration Using Parallel Self-Assembly of Chips With Cu–SnAg Microbumps and a Nonconductive Film

A new 3-D integration concept based on reconfigured wafer-to-wafer stacking is proposed. Using reconfigured wafer-to-wafer 3-D integration, many known-good dies (KGDs) can be simultaneously and precisely self-assembled by water surface tension onto a carrier wafer, which is called a reconfigured wafer. In addition, the KGDs on the reconfigured wafer can be transferred and bonded to another target wafer at the wafer level. The alignment accuracy is within 1 μm when 3 × 3-, 5 × 5-, 4 × 9,- or 10 × 10- mm2 chips are employed. To 3-D stack many KGDs in a batch process, we developed and employed a self-assembly multichip bonder. KGDs with 20- μm-pitch Cu-SnAg microbumps covered with a nonconductive film as a preapplied underfill material on their top surface were self-assembled right-side up, and then transferred to the corresponding target interposer wafer upside down. The resulting daisy chain with 500 Cu-SnAg microbumps exhibited ohmic contacts, and the resistance of ~ 40 mΩ/bump was sufficiently low for 3-D large-scale integration application.

Minimizing the local deformation induced around Cu-TSVs and CuSn/InAu-microbumps in high-density 3D-LSIs

One of the most serious reliability issues, the local deformation produced in the stacked LSI die/wafer with respect to the die thickness and the sub-surface structures formed after several stress-relief methods are systematically and extensively studied. From the electron backscatter diffraction (EBSD) analysis, a more than one degree (>1°) of local misorientation is created in the stacked LSI Si around μ-bump region. This induces a large tensile stress above the μ-bump region and relatively small compressive stress in the bump-space region, which leads to an enhancement in the n-MOSFET mobility in the μ-bump region and decrease in mobility at bump-space region. As compared to CuSn system, the InAu μ-bump induced huge amount of tensile stress (> 300 MPa) in the stacked LSI die even for the bonding temperature of 200 °C. The groove structures or scratches found at the background surface after stress relief by plasma etching (PE) or Dry Polishing (DP) severely deteriorates the device characteristics after stacking, owing to the enhanced local deformation as against the stress relief method of chemical mechanical polishing (CMP). Even after 500 cycles of temperature cycle (TC) test, a 20 μm-width Cu-TSV array with 40- μm pitch values induces not only around -570 MPa of compressive stress in the stacked LSI die, but also a large variation in the induced stress values between different TSVs in the same array. For the LSI die/wafer thickness of anything less than 50 μm, the Young modulus (E) and Hardness (H) of the thinned die no longer behaves like a bulk single crystal Si, which severely increases the reliability risks in the highly integrated 3D-LSIs.

New chip-to-wafer 3D integration technology using hybrid self-assembly and electrostatic temporary bonding

We proposed a new chip-to-wafer 3D integration technology using hybrid self-assembly and electrostatic temporary bonding. In the hybrid self-assembly-based chip-to-wafer 3D integration (HSA-CtW), liquid surface-tension-driven chip self-assembly is combined with high-speed robotic pick-and-place chip assembly and electrostatic multichip temporary bonding. Hybrid self-assembly can realize high-throughput chip assembly of above 10,000 chips/hour with a high alignment accuracy of <; 1 μm. The electrostatic multichip temporary bonding technique enabled stress-free direct bonding of self-assembled chips. We obtained good electrical characteristics from 3D stacked chips fabricated by HSA-CtW using Cu/SnAg microbumps and Cu-TSVs.