Wei-Chung Lo

Reliability tests for a three dimensional chip stacking structure with through silicon via connections and low cost

In order to achieve the shorter circuit design of multiple chips, three-dimensional (3D) packaging technologies with through silicon vias were developed to achieve high performance, low power consumption and small packaging size. In this paper, a PCB (Printed Circuit Board) processing compatible structure of three-dimensional chip stacking with low cost and easy fabrication will be shown. 3D and through Si via connections were formed by UV laser drilling technology. Laser drilling is a non-contact manufacture method and laser beam with high energy can be focused to a small spot (15 mum beam diameter) for material ablating and removing without mask used. Several processes are the keys to accomplish 3D stacking, such as wafer thinning process, through silicon via forming process, dielectric layer forming process, metallization process, and inter chips bonding process. By integration of the mentioned key processes, a 3D chip stacking structure with 10 layers was carried out. The thickness of chip was 100 mum. Daisy chain pattern was designed for the electrical measurement of 3D stacking structure. The testing results show that the resistance of multi- chip stacking structure is about 0.056 Omega/cm. Some reliability test, such as temperature cycling test and pressure cooker test were also done. These testing results verified this PCB processing compatible 3D chip stacking technology with low cost is a reliable structure for 3D SiP (System in Packaging) module application.

ABF-Based TSV Arrays With Improved Signal Integrity on 3-D IC/Interposers: Equivalent Models and Experiments

An Ajinomoto-Build-up-Film (ABF) material is proposed to manufacture through-silicon vias (TSVs) with better signal integrity and lower cost than that of conventional TSVs. The unique advantage of the ABF-based TSVs is that the isolation layer can be thicker than the conventional TSVs, and thus both the insertion loss and crosstalk of the ABF-based TSVs can be improved. An equivalent circuit model is given to predict the electrical behavior of the TSVs and to explain how ratio of the isolation layers thickness to the radius affects the signal integrity. The concept is demonstrated both in frequency- and time-domain simulations. Finally, a test sample of nine-stack ABF-based TSVs is fabricated and assembled. The scanning electron microscope figure supports that the ABF-based TSVs have a thickness-to-radius ratio of 0.667, which is much higher than the conventional TSVs ratio of about 0.1. The measurements also support the simulated results from the equivalent circuit model.

Novel crosstalk modeling for multiple through-silicon-vias (TSV) on 3-D IC: Experimental validation and application to Faraday cage design

An equivalent circuit model to characterize the crosstalk strength in multiple TSVs is newly proposed. In this model, all the values of lumped elements in the model are given in closed-form formulas. Therefore, the computation effort for constructing the model of multiple TSVs is much lower than other previous works. The accuracy is verified by the measurement for a nine stacked silicon chips and the full-wave simulation results. The proposed model is then utilized to the design for crosstalk mitigation. With the advantages of smaller occupied area (lower cost), a rhombus-grounded Faraday cage design is recommended with lower cost and similar performance compared to conventional Faraday cage concept.

A clamped through silicon via (TSV) interconnection for stacked chip bonding using metal cap on pad and metal column forming in via

To prevent potential yield loss, achieve TSV with higher aspect ratio, improve the bonding reliability, and reduce the process cost, a clamped through silicon via (C-TSV) interconnection for stacked chip bonding is proposed and developed in this paper. The metal cap on pad design can not only be a bonding layer for other stacked die on it, but also performs as a protection stopper for blind vias drilled from the wafer backside.

An innovative chip-to-wafer and wafer-to-wafer stacking

Abundant three-dimensional packaging technologies were developed for chip-to-wafer or wafer-to-wafer bonding, which employed through silicon interconnect to achieve the shortest circuit design of inter-chip or inter-wafer. In this paper, we focused on the wafer stacking technology by introducing silicon-through three-dimensional interconnect. The innovative structure as shown here is a new concept of three-dimensional integration of via-preformed silicon through wafers. Compared to the recently research of 3D chip-to-wafer or wafer-to-wafer stacking, it demonstrated of wafer stacking using this reliable design. The wafer/chip thickness used here was 150 mum and down to 50 mum. The result shows the benefits of this structure can provide more reliable wafer stacking without any voids. Not only the assembly accuracy of the joint between two chips/wafers can be reduced, but we can get improvement of the yield of the whole wafer during the wafer bonding process, even the thickness uniformity of the wafer is higher than 10%. The experiment confirmed that this newly low-cost interconnect technology could be a good candidate for both wafer stacking application and 3D SiP module

Development and characterization of low cost ultrathin 3D interconnect

With the economic criteria and efficiency concern increasing, abundant through-hole vertical interconnections are playing the more and more important role in this area. The properties and characterization of through-hole vertical interconnects are the key issue results in the RC delay during the reliability tests for 3D high-density module packaging. ERSO recently works mainly focuses on the investigation of the quality of low cost interconnect fabrication technology to meet the reliability requirement for 3D chip stacking interconnects. In this paper, we elucidate the interconnect technology for a stacked system in package (SiP) test vehicle. Compared to the vertical interconnects developed recently, we provide an extremely low cost solution for both of silicon hole drilling process and electrical isolation within the hole. A PCB compatible electroplating technology was followed to fill the hole and shows void-free and low resistance result during this work. The chip thickness used here can be 150/spl mu/m and down to 20 /spl mu/m and still provide outstanding interconnect reliability during bending and thermal cycling test. We confirmed that the low cost 3D interconnects are potentially candidate for 3D chip stacking packaging.

Process, assembly and electromigration characteristics of glass interposer for 3D integration

Glass interposer is proposed as a superior alternative to organic and silicon-based interposers for 3DIC packaging in the near future. Because glass is an excellent dielectric material and could be fabricated with large size, it provides several attractive advantages such as excellent electrical isolation, better RF performance, better feasibility with CTE and most importantly low cost solution. In this paper, we investigated the EM performance of Cu RDL line with glass substrate. Three different physical properties of glass materials were used for studying the EM performance of Cu RDL line. The used testing conditions are under 150~170 °C and 300~500mA. The glass type material with best performance was applied for glass interposer process integration and assembly investigation. Therefore, a wafer-level 300mm glass interposer scheme with topside RDLs, Cu TGVs, bottom side RDLs, Cu/Sn micro-bump and PBO passivation has been successfully developed and demonstrated in the study. The chip stack modules with glass interposer were assembled to evaluate their electrical characteristics. Pre-conditioning test was performed on the chip stacking module with the glass interposer to assess the reliability of the heterogeneous 3D integration scheme. All the results indicate that the glass interposer with polymer passivation can be successfully integrated with lower cost processes and assembly has been successfully developed and demonstrated in the study.

A Wafer-Level Three-Dimensional Integration Scheme With Cu TSVs Based on Microbump/Adhesive Hybrid Bonding for Three-Dimensional Memory Application

Thin wafer/chip stacking with vertical interconnect by a Cu through-silicon via (TSV) and a Cu/Sn microjoint is one of the candidates for 3-D integration. The insertion loss of the two-chip stack was evaluated with different TSV pitches, microbump diameters, and chip thicknesses to realize the signal transmission effects in high-speed digital signaling via TSV and microjoint interconnection. In addition, a wafer-level 3-D integration scheme with Cu TSVs based on Cu/Sn microbump and BCB adhesive hybrid bonding was demonstrated. Key technologies, including TSV interconnection, microbumping, hybrid bonding, wafer thinning, and backside RDL formation, were well developed and integrated to realize 3-D integration. This paper presents a complete study of the structure design, the process condition, and the electrical and reliability assessment of the wafer-level 3-D integration scheme. This 3-D integration scheme with excellent electrical performance and reliability provides a promising solution for 3-D memory application.

Energy release rate investigation for through silicon vias (TSVs) in 3D IC integration

The technology of 3D IC integration is highly probable to achieve the demand for high performance, better reliability, miniaturization and lower-priced portable electronic products. Since the through silicon via (TSV) is the heart in 3D IC integration architectures, the reliability issues of TSV interconnects should be extremely concerned. Due to the large thermal expansion mismatch among the Cu, Si, and SiO2, the induced thermal stresses and strains can occur and become the driving forces for failures in TSV interconnects. Hence, the stress analyses and failure mode investigation for TSVs are in urgent need. Among the typical failures, the mostly common failure type is delamination, which will be caused when lower energy release rate (ERR) or higher critical stresses at interfaces are presented. In this study, the finite element modeling (FEM) for a symmetrical single in-line copper filled TSV with redistribution layer is illustrated. Two kinds of horizontal cracks that embedded in the interface of SiO2 passivation and Cu seed layer (Cu pad delamination cases) are introduced to realize the interfacial ERR, where is also the critical stress area that observed from finite element analysis. The significance of design parameters such as crack length, TSV diameter, TSV pitch, depth of TSV, SiO2 thickness and Cu seed layer thickness are also brought up. The methodology of design of experiments (DoE) has been adopted to capture the most important mechanical parameters of the TSV to comprehend the corresponding ERR. It is believed that these results would be helpful to avoid delamination of TSV interconnects in 3D IC integration.

Development and characterization of rigid-flex interface

Flat panel displays (FPDs) are now getting more important role in the application of digital home and personal consumer electronics. For the future mobile application, the lack of flexibility and the decrement of weight will become the major challenges by using the glass substrate. The new choice of substrate material can provide the benefits to make the display become flexible that the current glass substrate is hard to compete with. Herein, we focused on the packaging approach by adopting the newly development technology of rigid-flex packaging by introducing flexible interconnect. There are two packaging approaches we explore the concept for flexible FPDs. One is the stretchable interconnect and the other is ultra thin die attached method. The results show we can achieve the 25% stretchable metal trace on flexible substrate, such as PU or PDMS and the resistance is keeping as low as 5 ohm/cm without any deformation. Besides, by choosing the suitable adhesives, we can also demonstrate the strong reliable interface during the bending test. The reliability test shows the intriguing structure can be applied for the flexible panel displays