Zhi-Cheng Hsiao

Characterization and reliability assessment of solder microbumps and assembly for 3D IC integration

In this investigation, Cu/Sn lead-free solder microbumps with 10μm pads on 20μm pitch are designed and fabricated. The chip size is 5mm × 5mm with thousands of microbumps. A daisy-chain feature is adopted for the characterization and reliability Assessment. After pattern trace formation, the microbump is fabricated on the trace by an electroplating technique. A suitable barrier/seed layer thickness is designed and applied to minimize the undercut due to wet etching but still achieve good plating uniformity. With the current process, the undercut is less than 1μm and the bump height variation is less than 10%. In addition, the shear test is adopted to characterize the bump strength, which exceeds the specification. Also, the Cu-Sn lead-free solder micro bumped chip is bonded on a Si wafer (chip-to-wafer or C2W bonding). Furthermore, the micro-gap between the bonded chips is filled with a special underfill. The shear strength of the bonded chips w/o underfill is measured and exceeds the specification. The bonding and filling integrity is further evaluated by open/short measurement, SAT analysis, and cross-section with SEM analysis. The stacked ICs are evaluated by reliability tests, including thermal cycling test (−55⇆125°C, dwell and ramp times = 15 min). Finally, ultra find-pitch (5μm pads on 10μm pitch) lead-free solder microbumping is explored.

Wafer Bumping, Assembly, and Reliability of Fine-Pitch Lead-Free Micro Solder Joints for 3-D IC Integration

In this investigation, Cu-Sn lead-free solder microbumps on 10-μm pads with a 20-μm pitch are designed and fabricated. The chip size is 5 × 5 mm with thousands of microbumps. A daisy-chain feature is adopted for the characterization and reliability assessment. After pattern trace formation, the microbump is fabricated on the trace by an electroplating technique. A suitable barrier/seed layer thickness is designed and applied to minimize the undercut due to wet etching but to still achieve good plating uniformity. With the current process, the undercut is less than 1 μm and the bump height variation is less than 10%. In addition, the shear test is adopted to characterize the bump strength, which exceeds the specification. Also, the Cu-Sn lead-free solder microbumped chip is bonded on an Si wafer using chip-to-wafer bonding technique. Furthermore, the microgap between the bonded chips is filled with a special underfill. The shear strength of the bonded chips without the underfill is measured and it exceeds the specification. The bonding and filling integrity is further evaluated by open/short measurement, scanning acoustic tomography analysis, and cross-section with scanning electron microscopy analysis. The stacked ICs are evaluated by reliability (thermal cycling) test (-55 to 125°C). Finally, ultrafine-pitch (5-μm pads on a 10-μm pitch) lead-free solder microbumping is explored.

Wafer-level 3D integration using hybrid bonding

In this paper, several material candidates for hybrid bonding technology in wafer-level 3D integration were investigated. Polymer materials, including BCB, SU-8, AL-Polymer, and polyimide (PI), were studied and then thermal-compression bonded between 150°C and 450°C. Characterization of bonded layer and evaluation of bond quality for these bonded wafers were investigated by Scanning Acoustic Tomograph (SAT), dicing test, shear test, and cross-sectional SEM. To understand the behavior and physics meaning of failure bonding, the mechanism is studied to explain the relation between bonding failure and material properties. In addition, samples with hybrid scheme were fabricated to perform hybrid bonding and realize the compatibility in whole processes. The demonstration of wafer-level 3D integration using hybrid bonding is significant to prove the manufacturability of 3D IC applications.

A Wafer-Level Three-Dimensional Integration Scheme With Cu TSVs Based on Microbump/Adhesive Hybrid Bonding for Three-Dimensional Memory Application

Thin wafer/chip stacking with vertical interconnect by a Cu through-silicon via (TSV) and a Cu/Sn microjoint is one of the candidates for 3-D integration. The insertion loss of the two-chip stack was evaluated with different TSV pitches, microbump diameters, and chip thicknesses to realize the signal transmission effects in high-speed digital signaling via TSV and microjoint interconnection. In addition, a wafer-level 3-D integration scheme with Cu TSVs based on Cu/Sn microbump and BCB adhesive hybrid bonding was demonstrated. Key technologies, including TSV interconnection, microbumping, hybrid bonding, wafer thinning, and backside RDL formation, were well developed and integrated to realize 3-D integration. This paper presents a complete study of the structure design, the process condition, and the electrical and reliability assessment of the wafer-level 3-D integration scheme. This 3-D integration scheme with excellent electrical performance and reliability provides a promising solution for 3-D memory application.

Wafer-to-wafer hybrid bonding technology for 3D IC

In this research, the wafer-level metal/adhesive hybrid bonding technology was developed to perform the 3D integration platform. Four kinds of polymer materials, BCB, SU-8, AL-Polymer, and PI, were evaluated as the bonding adhesive for hybrid collocation with metal. After realizing the bonding properties, the qualified ones were patterned on wafers, and sequentially bonded by metal bonding conditions. Two kinds of conditions were simulated, one is Cu-Sn eutectic bonding, and the other is Cu-Cu thermo-compression bonding. The compatibility between each polymer and metal was evaluated, and the application range of each material was established thereof. Furthermore, samples with hybrid scheme were fabricated to perform hybrid bonding and realize the compatibility in whole process. The micro-bump/Cu-pad size less than 20µm and thickness less than 5µm were designed for interconnection. The bonding quality and interface investigation on metal/adhesive were analyzed to make sure the interconnection and micro-gap filling between stacked wafers. The evaluation results of wafer-level hybrid bonding and material candidates will be disclosed in the paper.

Wafer-level 3D integration with Cu TSV and micro-bump/adhesive hybrid bonding technologies

Cu TSV combination with Cu/Sn micro-joint to form vertical interconnection is a good alternative for 3D integration. The insertion loss of two chip stack was evaluated by simulation to realize the signal transmission effects in high speed digital signaling via TSV and micro-joint interconnect. To satisfy the throughput and cost requirement for mass production in future, a wafer-level 3D integration scheme with Cu TSVs based on Cu/Sn micro-bump and BCB adhesive hybrid bonding was demonstrated. Key techniques including TSV fabrication, micro-bumping, hybrid bonding, wafer thinning and backside RDL formation were well developed and integrated to perform the 3D integration scheme. This paper presents a complete study of structure design, process condition, electrical and reliability assessment of the wafer-level 3D integration scheme. The 3D integration scheme was assessed to be with excellent electrical performance and reliability, and is potentially to be applied for 3D IC applications.

A Novel 3D Integration Scheme for Backside Illuminated CMOS Image Sensor Devices

A novel backside-illuminated CMOS image sensor (BSI-CIS) scheme and process are developed and demonstrated. This innovative scheme can be realized without fusion oxide bonding and through-silicon via (TSV) fabrication. This wafer-level TSV-less BSI-CIS scheme includes transparent ultrathin silicon (~ 3.6 μm) and uses several bonding technologies. The characterization and assessment results indicate that the integration scheme possesses excellent electrical integrity and reliability. In addition, good quality results of the image functional test demonstrate the excellent performance of this scheme. This novel scheme also provides a realizable low-cost solution for the next-generation CIS and further 3-D novel BSI-CIS scheme.

Low-cost TSH (through-silicon hole) interposers for 3D IC integration

In this investigation, a SiP (system-in-package) which consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top- and bottom-side (a real 3D IC integration) is studied. Emphasis is placed on the fabrication of a test vehicle to demonstrate the feasibility of this SiP technology. The design, materials, and process of the top-chip, bottom-chip, TSH interposer, and final assembly will be presented. Shock and thermal cycling tests will be preformed to demonstrate the integrity of the SiP structure.

Cu/BCB hybrid bonding with TSV for 3D integration by using fly cutting technology

In this research, the wafer level Cu/BCB hybrid bonding with TSV for 3D integration by using fly cutting technology is proposed. As we know Cu bump surface is rough by electroplating, and BCB is spin-coated on Cu bump wafer induced high topography. Cu bump surface roughness and Cu/BCB co-planarization are improved by fly cutting to achieve good Cu to Cu and BCB to BCB bonding interface without any large bonding voids at 250°C for 30min, and the result of the bonding strength is evaluated by shear test. TSV fabrication, micro-bumping, hybrid bonding, wafer thinning and backside RDL formation are well developed and integrated to perform the 3D integration platform. Cu/BCB hybrid bonding with TSV for 3D integration is successfully developed and demonstrated in this paper.

Wafer bumping, assembly, and reliability assessment of μbumps with 5μm pads on 10μm pitch for 3D IC integration

In this study, ultra fine pitch Cu/Sn lead-free solder microbumps are investigated. Emphasis is placed on wafer bumping, assembly, and reliability of microbumps for 3D IC integration applications. The test vehicle consists of a chip (5mm × 5mm) with 3,200 pads. The pad size is 5μm in diameter and on 10μm pitch. A daisy-chain feature is adopted for the characterization and reliability Assessment. After pattern trace formation, the microbump is fabricated on the trace by an electroplating technique. The wet-etching process is used for the etching of seed layer. A suitable barrier/seed layer thickness is designed and applied to minimize the undercut due to wet etching but still achieve good plating uniformity. In addition, the shear test has been adopted to characterize the bump strength, which exceeds the specification. After wafer bumping and characterization of the microbumps, the Moores law wafer is dicing into individual chips for chip-to-chip (C2C) bonding of the micro solder joints. The C2C bonding is a flux thermocompression process with a peak temperature of 260°C. The microstructure analyses reveal that the ultra fine pitch micro solder joint can be considered as an intermetallic compound (IMC) joint composed of Cu6Sn5 and a few residual solder compounds.