Chengqing Wei

Rigorous Surface-Potential Solution for Undoped Symmetric Double-Gate MOSFETs Considering Both Electrons and Holes at Quasi NonEquilibrium

This paper presents a rigorously-derived analytical solution of the Poisson equation with both electrons and holes in pure silicon, which is applied to the analysis of undoped symmetric double-gate transistors. An implicit surface-potential equation is obtained that can be solved by a second-order Newton-Raphson technique along with an appropriate initial guess. Within the assumption of holes at equilibrium that is being used in the existing literature, the new results, when compared with the models based on one carrier, reveal that missing the other carrier in the formulation results in a singularity in the gate capacitance exactly at flatband, which may give trouble for high-frequency analysis, although the errors in surface potentials are below the nano-volt range for all gate voltages. However, the solution without assuming constant hole imref, as presented in this paper for the first time, further pinpoints the inadequacy in existing theories of surface-potential solutions in double-gate MOSFETs with undoped thin bodies, although its application to transport solutions of terminal current/charge models depends highly on the type of source/drain structures and contacts.

Investigation of Low-Frequency Noise in Silicon Nanowire MOSFETs in the Subthreshold Region

The low-frequency noise (LFN) in the subthreshold region of both n- and p-type gate-all-around silicon nanowire transistors (SNWTs) is investigated. The measured drain-current noise spectral density shows that the LFN in this regime can be well described by the mobility-fluctuation model due to the volume-inversion conduction behavior, and the Hooge parameter is extracted. The LFN in the SNWTs with channels oriented in lang010rang and lang110rang directions is compared. It shows that the observed mobility enhancement in the lang010rang direction for p-type transistors leads to a corresponding increase of the LFN level in the lang010rang direction compared with that in the lang110rang direction.

Investigation of Low-Frequency Noise in N-Channel FinFETs From Weak to Strong Inversion

This paper presents the low-frequency noise (LFN) characteristics of symmetric double-gate n-FinFETs from weak to strong inversion at low drain bias. The noise-generation mechanism is investigated. The measured drain-current noise spectral density shows that LFN in the weak-inversion subthreshold region can be well described by the mobility-fluctuation model due to volume-inversion conduction behavior, which is very different from those normally observed in the bulk NMOS. The analytical expression for the drain-current noise spectral density is derived, with the Hooge parameter alphaH being extracted. In the strong-inversion linear region, the gate-voltage dependence of the room-temperature noise data agrees with the number-fluctuation model, but the slope of the frequency dependence is less than one. To determine the causes of the observed deviation from the unity slope, detailed measurements of the temperature dependence of the noise power spectra are performed, and results from two devices are presented in this paper. It is found that both the magnitude and the frequency dependence of the drain-voltage noise spectral density vary greatly in the range between 223 K and 383 K. The experimental results are compared with two models derived based on the Dutta-Horn and the McWhorter models. It is shown that the thermal-activation model of Dutta-Horn is more convincing than the latter, which shows that the noise is due to the capture and emission of carriers by oxide traps through thermal activation. The surface trap density at specific activation energy is extracted.

Impact of Gate Electrodes on

The low-frequency (1/f) noise of gate-all-around silicon nanowire transistors (SNWTs) with different gate electrodes (poly-Si gate, doped fully silicided (FUSI) gate, and undoped FUSI gate) is studied in the strong-inversion linear region. It shows that the gate electrodes have a strong impact on the 1/f noise of the SNWTs. The highest noise is observed in the SNWTs with a poly-Si gate, compared to their FUSI-gate counterparts. The observations are explained according to the number fluctuation with correlated mobility fluctuation theory by assuming that the correlated mobility scattering is better screened in the case of an undoped FUSI gate. However, the doped FUSI gate with silicidation-induced impurity segregation at the gate/SiO2 interface gives rise to extra mobility scattering.

\hbox{1}/f

This paper presents a new concept for the MOSFET saturation voltages at the drain and source sides referenced to bulk, and applies them to the popularly used smoothing functions for the effective drain-source voltage (Vds,eff ). The proposed model not only builds in physically all the terminal-bias variations, but is also extended to include source/drain asymmetry in real devices in a single-core compact model. The new model resolves a key bottleneck in existing models for passing the Gummel symmetry test (GST) in higher order derivatives, which has to be traded off for the geometry-dependent Vds,eff smoothing parameter. The complete drain-current model, including the effects of velocity saturation and overshoot as well as source/drain series resistance, has also been reformulated with the same ldquobulk-referencingrdquo concept. It is shown that the proposed model passes the GST in all higher order derivatives without any constraint on the value of the smoothing parameter. It also demonstrates potential extension to modeling asymmetric MOSFETs, which is becoming an important model capability.

Noise of Gate-All-Around Silicon Nanowire Transistors

A non-charge-sheet surface-potential-based compact drain-current model for long-channel undoped gate-all-around (GAA) silicon-nanowire (SiNW) MOSFETs is developed. The surface-potential equation is derived from cylindrical Poisson equation for undoped silicon and solved iteratively with a very good initial guess to reach equation residue below 10-16 V within a few iterations. The single-piece current equation is derived and validated with numerical simulations for all operation regions without any fitting parameters. The results show that the proposed model can be used for bench-marking long-channel SiNW models, and demonstrate a first step towards a practical SiNW model for inclusion of various short-channel and quantum-mechanical effects.

A Compact Model Satisfying Gummel Symmetry in Higher Order Derivatives and Applicable to Asymmetric MOSFETs

In existing impact-ionization current (Jsub) models for short-channel MOSFETs, various models for the characteristic ionization length (I) or the velocity-saturation region length (lsat) have been developed by using the polynomial-fitting method in order to model the bias dependence of the maximum electric field (Em) in the channel. This paper proposes a bias-voltage- and gate-length-dependent effective maximum electric field (Em,eff) based on energy-balance equation, aimed at obtaining an accurate expression of Em to increase the accuracy of the Isub model for deep submicrometer devices. This new method overcomes the complicated modeling of I, avoids the extraction of different fitting constants for different devices, and enables unique extraction of the impact-ionization coefficients (A and B) for different devices. This improved model demonstrates excellent agreements with the numerical data of nMOSFETs from a 90-nm-technology wafer file. Only one unique set of parameters is needed to fit the data from devices with different biases and lengths for the same technology node. Moreover, since the lattice temperature (Tl) is built in the formulation of Em,eff, a compact Isub model with self-lattice-heating is developed, which also accounts for the excess substrate current observed in the SOI devices due to carrier heating in the channel.

A rigorous surface-potential-based I-V model for undoped cylindrical nanowire MOSFETs

This paper describes an alternative way of driving the complementary metal-oxide-semiconductor (CMOS) device into different drain-current levels for low-frequency-noise (LFN) characterization. A floating-gate (FG) test structure that constructs the characterized MOSFET with an extra control gate is proposed. A metal-insulator-metal (MIM) capacitor is used to construct this control gate. Instead of applying different input-dc-bias supplies for the gate terminals of the MOSFETs, the device is directly programmed to the drain-current levels of interest by CHARGE/DISCHARGE operations. In this case, no gate bias is required in the drain-current noise measurement, so that any potential disadvantages from gate-bias supply networks that would prevent accurate noise measurements are totally excluded. The LFN measurement results demonstrating the feasibility of the proposed test structure are also reported.

A New Impact-Ionization Current Model Applicable to Both Bulk and SOI MOSFETs by Considering Self-Lattice-Heating

This paper reviews the basic governing equations for a double-gate/gate-all-around (DG/GAA) MOSFET in a generic and unified description. Starting from generic Poisson solution and input voltage equation, a paradigm shift with ground-reference and source/drain by label is proposed, which is essential in formulating equations for DG FinFETs without body contact. The unified regional modeling (URM) approach is used for unified surface-potential solutions, and is applied to demonstrate Gummel symmetry in doped DG with partial to full-depletion operations.

Test Structure for Characterization of Low-Frequency Noise in CMOS Technologies

This paper presents the characteristics of ideal double-gate/gate-all-around (DG/GAA) MOSFETs, including the long/short-channel and thin/thick-body effects. A unified compact model (Xsim) based on the unified regional modeling (URM) approach for the generic DG/GAA MOSFET is used to demonstrate the expected behaviors, which should be included in the core model describing such emerging devices.