Zhaomin Zhu

Surface-Potential Solution for Generic Undoped MOSFETs With Two Gates

We present a rigorously derived analytical Poisson solution for undoped semiconductors and apply the general solution to generic MOSFETs with two gates, unifying different types such as silicon-on-insulator (SOI) and symmetric and asymmetric double gate (s-DG and a-DG) structures. The Newton-Raphson method is used to solve surface-potential equations resulting from the application of boundary conditions to the general Poisson solution, with an initial guess that is very close to the exact solution. The universal initial guess can be used as an approximate explicit solution for fast evaluation, while the iterative solution can be used for benchmark tests. The results demonstrate the unification of surface-potential solutions having an accuracy of 10-15 V for SOI, a-DG, and s-DG MOSFETs, which are achieved within two to six iterations. Furthermore, the explicit solution yields less than 3.5% error for back-to-front-gate oxide thickness ratios larger than 25

Rigorous Surface-Potential Solution for Undoped Symmetric Double-Gate MOSFETs Considering Both Electrons and Holes at Quasi NonEquilibrium

This paper presents a rigorously-derived analytical solution of the Poisson equation with both electrons and holes in pure silicon, which is applied to the analysis of undoped symmetric double-gate transistors. An implicit surface-potential equation is obtained that can be solved by a second-order Newton-Raphson technique along with an appropriate initial guess. Within the assumption of holes at equilibrium that is being used in the existing literature, the new results, when compared with the models based on one carrier, reveal that missing the other carrier in the formulation results in a singularity in the gate capacitance exactly at flatband, which may give trouble for high-frequency analysis, although the errors in surface potentials are below the nano-volt range for all gate voltages. However, the solution without assuming constant hole imref, as presented in this paper for the first time, further pinpoints the inadequacy in existing theories of surface-potential solutions in double-gate MOSFETs with undoped thin bodies, although its application to transport solutions of terminal current/charge models depends highly on the type of source/drain structures and contacts.

A Compact Model Satisfying Gummel Symmetry in Higher Order Derivatives and Applicable to Asymmetric MOSFETs

This paper presents a new concept for the MOSFET saturation voltages at the drain and source sides referenced to bulk, and applies them to the popularly used smoothing functions for the effective drain-source voltage (Vds,eff ). The proposed model not only builds in physically all the terminal-bias variations, but is also extended to include source/drain asymmetry in real devices in a single-core compact model. The new model resolves a key bottleneck in existing models for passing the Gummel symmetry test (GST) in higher order derivatives, which has to be traded off for the geometry-dependent Vds,eff smoothing parameter. The complete drain-current model, including the effects of velocity saturation and overshoot as well as source/drain series resistance, has also been reformulated with the same ldquobulk-referencingrdquo concept. It is shown that the proposed model passes the GST in all higher order derivatives without any constraint on the value of the smoothing parameter. It also demonstrates potential extension to modeling asymmetric MOSFETs, which is becoming an important model capability.

Explicit compact surface-potential and drain-current models for generic asymmetric double-gate metal-oxide-semiconductor field-effect transistors

In this paper, explicit surface potentials for undoped asymmetric-double-gate (a-DG) metal–oxide–semiconductor field-effect transistors (MOSFETs) suitable for compact model development are presented for the first time. The model is physically derived from Poissons equation in each region of operation and adopted in a unified regional approach. The proposed model is physically scalable with oxide/channel thicknesses and has been verified with generic implicit solutions for independent gate biases as well as for different gate/oxide materials. The model is extendable to silicon-on-insulator (SOI) and symmetric-DG (s-DG) MOSFETs. Finally, a continuous, explicit drain-current equation has been derived on the basis of the developed explicit surface-potential solutions.

A rigorous surface-potential-based I-V model for undoped cylindrical nanowire MOSFETs

A non-charge-sheet surface-potential-based compact drain-current model for long-channel undoped gate-all-around (GAA) silicon-nanowire (SiNW) MOSFETs is developed. The surface-potential equation is derived from cylindrical Poisson equation for undoped silicon and solved iteratively with a very good initial guess to reach equation residue below 10-16 V within a few iterations. The single-piece current equation is derived and validated with numerical simulations for all operation regions without any fitting parameters. The results show that the proposed model can be used for bench-marking long-channel SiNW models, and demonstrate a first step towards a practical SiNW model for inclusion of various short-channel and quantum-mechanical effects.

General analytical poisson solution for undoped generic two-gated metal-oxide-semiconductor field-effect transistors

We present a general analytical solution to the Poisson equation for undoped semi-conductors. This general Poisson solution is then applied to generic dual-gate metal-oxide- semiconductor field-effect transistors (MOSFETs), unifying different types including silicon-on-insulator, and symmetric and asymmetric double-gate MOSFETs. Newton-Raphson (NR) algorithm is called to solve the resulting surface-potential equation. An exact solution is proposed making the NR algorithm computationally very efficient. While the universal initial guess can be used as an approximate solution for fast evaluation, the iterative results by NR algorithm are useful for benchmark tests.

A scalable compact model for generic HEMTs in III–V/Si co-integrated hybrid design

In this paper, we present a unified compact model (Xsim) that is based on drift-diffusion/surface-potential (DD/SP) formalism for Si-bulk/SOI MOSFETs by incorporating a unified 2-dimensional electron gas (2DEG) model for extension to generic III-V MIS-HEMTs. The model has been validated with TCAD and experimental data for GaN-based HEMTs with nanometer gate lengths. Digital (inverter/ring-oscillator) and analog (cut-off frequency) circuit performance prediction based on nanometer GaN devices are also demonstrated. The ultimate goal is to develop a unified scalable model for III-V/Si co-integrated hybrid circuit design.

Physics based scalable MOSFET mismatch model for statistical circuit simulation

MOSFET mismatch model based on BSIM3v3 for a CMOS 0.13 mum technology using backward propagation of variance (BPV) methodology coupled with Pelgrom model basis was developed. Test structures were carefully designed for intrinsic MOSFET drain current mismatch characterisation under 4 different gate voltages that vary from weak to strong inversion for both linear and saturation regions. Monte Carlo MOSFET matched pair simulation using HSPICE was performed for model verification. The model was shown to be scalable for different biases and sizes and physically consistent in predicting the MOSFET mismatch in threshold voltage in linear and saturation regions.

New challenges in MOS compact modeling for future generation CMOS

As bulk-MOS technology is approaching its fundamental limit, non-classical devices such as multiple-gate (MG) and silicon-nanowire (SiNW) transistors emerge as promising candidates for future generation device building blocks. This trend poses new challenges to developing a compact model suitable for these new device structures and requires a paradigm shift in the core model structure. Conventional bulk-MOS models are based on four-terminal unipolar conduction in a doped channel with ideal symmetrical PN-junction source/drain contacts. In MG/NW MOSFETs, however, the device becomes three-terminal with undoped channel and possible bipolar conduction, and source/drain contacts become an integral part of intrinsic channel. Source/drain asymmetry, either intentional or unintentional, in a theoretically symmetric MOSFET also becomes important to be captured in a compact model, which is nontrivial in a model that depends on terminal source/drain swapping at the circuit level. This paper discusses these new challenges and demonstrates solutions based on the unified regional modeling (URM) approach.

Impact of BEOL, multi-fingered layout design, and gate protection diode on intrinsic MOSFET threshold voltage mismatch

Continued scaling down of MOSFETs, compounded with limitation in process variation control capabilities, has made MOSFET mismatch more significant for advanced technologies. In order to prevent over compensating for MOSFET mismatch in design margin, it is important to characterize the intrinsic MOSFET mismatch accurately. In this paper, test structures are designed to study the influence of back end of line (BEOL), multi-fingered layout, and gate protection diode (GPD) on MOSFET threshold voltage mismatch characterization.