Roger A. Booth

A novel, low-cost deep trench decoupling capacitor for high-performance, low-power bulk CMOS applications

We present an overview and electrical results for a novel deep trench decoupling capacitor. The process of this decoupling capacitor borrows from the regular embedded DRAM trench process, but with significant process simplification for decoupling use which provide reduced cost and reduced process cycle time. This capacitor can provide significant chip-level area savings, using only 1/8 silicon real estate to fabricate the same capacitance as standard planar gate oxide capacitors. Additionally, the trench decap demonstrates a dramatic improvement in leakage compared to standard planar gate oxide capacitors - as much as 105 improvement in leakage can be realized using trench decaps instead of conventional planar decap designs.

A 45nm low power bulk technology featuring carbon co-implantation and laser anneal on 45°-rotated substrate

This paper presents a cost-effective low power 45 nm bulk technology platform, primarily designed to serve the wireless multimedia and consumer electronics need. This technology platform features carbon co-IIP in the nMOS halo, laser annealing scheme, stress liner on the 45°-rotated wafer (<100>) for process simplicity to achieve high device performance and low leakage together. Drive current as high as 650/320 uA/um at Ioff of 0.5 nA/um with Vdd=1.1V has been achieved for both NMOS and PMOS respectively. Ring oscillator speed (FO=1) has been boosted up by 30% with the device optimization. SRAM Vt mismatch is also improved by 10% with carbon co-IIP with good SRAM characteristics and low leakage current in 0.299 um2 cell.

Z-Axis NEXT & FEXT Reduction: Broadside Coupling Reduction Using Cu Vacuum Deposition in Mesh Reference Circuits

Signal integrity (SI) and cross-talk concerns play significant roles constraining design options for low-cost, high speed interconnect solutions. The electrical packaging and signal integrity engineers must focus on SI and noise concerns even though the cost pressure continues to drive for the use of lower cost packaging along with increased overall function. Target cost trends have caused designers to investigate chip-on-flex and other integrated flexible circuit interconnect solutions. A significant portion of all flexible circuit designs utilize mesh referencing planes to improve mechanical flexibility or achieve target characteristic impedances. These resulting geometries have the potential to create compromised transmission line topologies and negatively impact SI. This paper will introduce the design performance compromises involved with mesh reference plane constructs, their impact on Signal Integrity, the challenging simulation analysis, and product design. Specifically, this research will investigate the application of copper vacuum deposition as a potential method to address these performance trade-offs associated with typical mesh reference plane topologies .